Smallest V<inf>th</inf> variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate

BSIM-IMG with improved surface potential calculation recipe

“…In this section we have shown the BSIM-IMG model validation with measured data at 50nm technology node [4]. AC and DC synunetry tests are also described in this section.…”

“…Model's C-V characteristics validation with experimental data [4] is shown in Figure 3 for NMOS and PMOS at IV bg l = O.OV and IVds l =O.OV from long to short device dimensions. Model has correct behavior for the capacitance in all regions of operation from depletion to inversion.…”

“…FDSOI MOSFET has lightly doped body which reduces process induced variability and increases yield [3], [4], [5], [6]. Threshold voltage tuning via back biasing through thin BOX provides multi-threshold (High-Vt and Low-Vt) flavor on same chip which provides facility to have high performance at low power consumption [7], [8], [9], [lO].…”

Ultralow-power LSI Technology with Silicon on Thin Buried Oxide (SOTB) CMOSFET

“…To solve the V th variation problem due to RDF and satisfy the demand from circuit designers, we have proposed the SOTB CMOSFET (Tsuchiya et al, 2004;Ishigaki et al, 2008;Morita et al, 2008). Figure 1 shows a schematic cross-section of the SOTB structure.…”

“…The nominal V th cumulative probability plot (not shown) of SOTB CMOSFETs indicates that the distribution is random and SCE is suppressed even down to 50 nm (Morita et al, 2008).…”