SoC connectivity specification extraction using incomplete RTL design: An approach for Formal connectivity Verification

Saafan, Haytham; El-Kharashi, M. Watheq; Salem, Ashraf

doi:10.1109/idt.2016.7843024

Cited by 9 publications

(5 citation statements)

References 4 publications

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“…RELATED WORK SoC interface connectivity is studied in [1,2]. Using formal check is discussed in [1,3], the advantage of formal check is obvious compared to conventional simulation techniques.…”

Section: IImentioning

confidence: 99%

“…Using formal check is discussed in [1,3], the advantage of formal check is obvious compared to conventional simulation techniques. The characteristics of RTL code is concluded in [3,4].…”

Section: IImentioning

confidence: 99%

“…The characteristics of RTL code is concluded in [3,4]. In [1] Re-use techniques is discussed, which is necessary in order to shorten the design cycle. At the time [2] summaries two simple generation method for checking connectivity of interface, the one is using a text editor by providing the formal to actual connections, the other is using script or program traverses the set of design modules, attempts to make connections based on specified rules.…”

Section: IImentioning

confidence: 99%

“…Compare with dynamic simulation, formal check does not need waveform simulation, this means that the state space could be traverse completely through mathematical method, and more time could be saved. In addition, the issues beyond functional design could be found at early stage of RTL, thus the turnaround time will be cut down [1]. Formal check methods include: syntax check, linting check, cross-clock domain check and formal verification [9].…”

Section: Introductionmentioning

confidence: 99%

“…Re-use past designs is necessary in order to shorten the design cycle by re-using previous work or component libraries. But most of errors during the integration of new devices on the system are due to incorrect connections, cause by inevitable artificial reason [1]. Connection includes module internal link type and pin to pin type between modules, which usually define in top-level modules.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

An Approach for Checking RTL Design Signal Sources and Destinations

Song¹,

Chen²,

Guo³

2017

Proceedings of the 2017 International Conference on Electronic Industry and Automation (EIA 2017)

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Abstract-Formal check provides a method for detecting problems of SoC design in early time of verification. Looking at SoC design issues, most of design integration errors come from modules connectivity. Combining above two points, this paper descripts an approach check signal connectivity with formal check method. The approach parses Verilog HDL RTL code through a program, which writes by script language Perl, to analysis signals connectivity. It's helpful for both SoC designer and verification engineer.

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Section: IImentioning

confidence: 99%

“…Using formal check is discussed in [1,3], the advantage of formal check is obvious compared to conventional simulation techniques. The characteristics of RTL code is concluded in [3,4].…”

Section: IImentioning

confidence: 99%