SoC-FPGA-Based Implementation of Iris Recognition Enhanced by QC-LDPC Codes

Ma, Longyu; Sham, Chiu-Wing

doi:10.1109/icfpt47387.2019.00075

Cited by 6 publications

(2 citation statements)

References 16 publications

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“…Other options offered by reconfigurable logic manufacturers include the use of newgeneration System-on-Chips (SoCs) as the ZynQ family from Xilinx [17] or the Cyclone V SE [18] from Intel, including one or more ARM cores [19]. In this case, these are also quite complex 32-bit microprocessors, thus, requiring off-chip memory if low-cost devices are targeted.…”

Section: Introductionmentioning

confidence: 99%

Dracon: An Open-Hardware Based Platform for Single-Chip Low-Cost Reconfigurable IoT Devices

et al. 2022

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The development of devices for the Internet of Things (IoT) requires the rapid prototyping of different hardware configurations. In this paper, a modular hardware platform allowing to prototype, test and even implement IoT appliances on low-cost reconfigurable devices is presented. The proposed platform, named Dracon, includes a Z80-clone microprocessor, up to 64 KB of RAM, and 256 inputs/outputs (I/Os). These I/Os can be used to connect additional co-processors within the same FPGA, external co-processors, communications modules, sensors and actuators. Dracon also includes as default peripherals a UART for programming and accessing the microprocessor, a Real Time Clock, and an Interrupt Timer. The use of an 8-bit microprocessor allows the use of the internal memory of the reconfigurable device as program memory, thereby, enabling the implementation of a complete IoT device within a single low-cost chip. Indeed, results using a Spartan 7 FPGA show that it is possible to implement Dracon with only 1515 6-input LUTs while operating at a maximum frequency of 80 MHz, which results in a better trade-off in terms of area and performance than other less powerful and less versatile alternatives in the literature. Moreover, the presented platform allows the development of embedded software applications independently of the selected FPGA device, enabling rapid prototyping and implementations on devices from different manufacturers.

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Section: Introductionmentioning

confidence: 99%

Dracon: An Open-Hardware Based Platform for Single-Chip Low-Cost Reconfigurable IoT Devices

et al. 2022

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“…Thanks to the widespread exploitation of LDPC codes since decades ago, QC-LDPC codes are proved to be one of the most promising candidates for having their structures optimized for hardware [33]. However, there are not many studies exploring the implementation of QC-LDPC codes into biometric systems [34]. emphasizes how to build a mechanism to exchange information between a processor and QC-LDPC decoders and shows the utilization of each modules in its design, while calculates the Hamming Distance between LDPC-based and non-LDPC-based iris recognition in a fixed threshold [35].…”

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confidence: 99%

An Embedded Iris Recognition System Optimization using Dynamically ReconfigurableDecoder with LDPC Codes

Sham

et al. 2021

Preprint

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Extracting and analyzing iris textures for biometric recognition has been extensively studied. As the transition of iris recognition from lab technology to nationscale applications, most systems are facing high complexity in either time or space, leading to unfitness for embedded devices. In this paper, the proposed design includes a minimal set of computer vision modules and multi-mode QC-LDPC decoder which can alleviate variability and noise caused by iris acquisition and follow-up process. Several classes of QC-LDPC code from IEEE 802.16 are tested for the validity of accuracy improvement. Some of the codes mentioned above are used for further QC-LDPC decoder quantization, validation and comparison to each other. We show that we can apply Dynamic Partial Reconfiguration technology to implement the multi-mode QC-LDPC decoder for the iris recognition system. The results show that the implementation is power-efficient and good for edge applications.

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An Iris Recognition System Implementation with Error Correction Capability by Reusing WiFi Standard LDPC Codes

Zhong

Sham

et al. 2020

2020 IEEE 9th Global Conference on Consumer Electronics (GCCE)

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SoC-FPGA-Based Implementation of Iris Recognition Enhanced by QC-LDPC Codes

Cited by 6 publications

References 16 publications

Dracon: An Open-Hardware Based Platform for Single-Chip Low-Cost Reconfigurable IoT Devices

Dracon: An Open-Hardware Based Platform for Single-Chip Low-Cost Reconfigurable IoT Devices

An Embedded Iris Recognition System Optimization using Dynamically ReconfigurableDecoder with LDPC Codes

An Iris Recognition System Implementation with Error Correction Capability by Reusing WiFi Standard LDPC Codes

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