SOC Test Architecture and Method for 3-D ICs

Lo, Chih-Yen; Hsing, Yu-Tsao; Denq, Li-Ming; Wu, Cheng‐Wen

doi:10.1109/tcad.2010.2051732

Cited by 28 publications

(6 citation statements)

References 10 publications

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“…Lo et al [19] proposes a test architecture for 3D-SICs, considering pre-bond, post-bond, as well as TSVbased interconnect testing. The proposed architecture reuses the test wrapper of cores embedded in the various dies to support modular testing in 3D-SICs, achieving a small area cost.…”

Section: Related Prior Workmentioning

confidence: 99%

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

et al. 2011

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Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows prebond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units, which allows flexible optimization of the 3D-SIC test flow and provides yield monitoring and first-order fault diagnosis. The architecture builds on and reuses existing DfT hardware at the core, die, and product level.

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Section: Related Prior Workmentioning

confidence: 99%

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

et al. 2011

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show abstract

“…Lo et al [20] propose a test architecture for 3D-SICs, considering prebond, post-bond, as well as TSV-based interconnect testing. The proposed architecture reuses the test wrappers of cores embedded in the various dies to support modular testing in 3D-SICs, achieving a small area cost.…”

Section: Related Prior Workmentioning

confidence: 99%

“…With respect to DfT for 3D-SICs, there is recent prior work on scan chain optimization [14], Test Access Mechanism (TAM) optimization [15][16][17], and the definition of DfT architectures [18][19][20][21]. All prior work focuses on 3D-SICs consisting of a single "tower", i.e., only one die per stack level.…”

Section: Introductionmentioning

confidence: 99%

DfT Architecture for 3D-SICs with Multiple Towers

Chi

Marinissen

Goel

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) provide attractive benefits such as smaller form factor, higher performance, and lower power. So far, prior work on Design-for-Testability (DfT) only focused on 3D-SICs consisting of a single "tower", i.e., a 3D-SIC in which each stack level contains exactly one die. 3D stacking technology allows to place multiple dies on top of a common base die, resulting in 3D-SICs with multiple "towers". This paper presents a generic DfT architecture for 3D-SICs having any number of "towers", possibly including "sub-towers". We also present efficient test control mechanisms. Experimental results show that the proposed architecture has a negligible area cost for medium-sized and larger industrial designs, and therefore provides a cost-effective test solution for 3D-SICs.

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“…It makes the schedule generation difficult as it is necessary to ensure power limit validation at every time instant of the schedule. Some initial works in 3D-SIC testing have proposed test architecture design [3], while some other works considered test optimization and test scheduling [4], [5] of the entire stack. However, these works do not consider the power constraint during test optimization.…”

Section: Introductionmentioning

confidence: 99%

Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints

Karmakar

Agarwal

Chattopadhyay

2015

2015 IEEE 24th Asian Test Symposium (ATS)

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This paper presents a test infrastructure development and test scheduling strategy for 3D-SICs under resource (test pins and TSVs) and power constraints. Depending upon the various scheduling restrictions, two test scheduling strategies have been proposed with an objective to minimize the overall test time (T T ) of the stack. A step-by-step approach deals with the individual dies separately and develops power-restricted test schedules for each die and finally decides test concurrency between the dies satisfying the resources and power limits of the stack. Particle Swarm Optimization (PSO) based meta search technique has been used to select the resource allocation and power distribution to individual dies and also their internal test schedules. Incorporation of PSO in two stages of optimization produces a notable reduction in the overall test time of the SIC. Another integrated approach uses PSO to generate powerconstrained test schedule of the entire SIC in a single optimization step. Integrated approach produces better results than the stepby-step approach because of its higher flexibility with lesser restrictions. User may select any of the scheduling strategies depending upon the scheduling criteria.

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SOC Test Architecture and Method for 3-D ICs

Cited by 28 publications

References 10 publications

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

DfT Architecture for 3D-SICs with Multiple Towers

Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints

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