Soft-core reduction methodology for SIMD architecture: OPENRISC case study

Abstract

Multi-Processor Systems on Chip (MPSoCs) have been proposed as a promising solution for the increasing demand of computational power required for recent application. The parallelization through SIMD (single instruction/multiple data) architectures has been a proven solution to speed up the processing of the recent application that exhibit massive amounts of data parallelism. The level of parallelism impacts the SIMD architecture performance and it is closely related to the design of the processing element. In this context this paper presents a new design methodology of designing processing element for SIMD architecture. The scope of this work is to reduce the pipeline stages of the soft-core processor to reduce the size of the PEs and so that to built up a high level parallelism architecture.I.

FPGA-based many-core System-on-Chip design

“…Moreover, the increasing gap between design productivity and chip 28 complexity requires new design methods. Nowadays, the recent evolution of silicon integration technol- 29 ogy, on the one hand, and the wide usage of reusable Intellectual Property (IP) cores and FPGAs (Field 30 Programmable Gate Arrays), on the other hand, are attractive solutions to meet these challenges and 31 reduce the time-to-market. The objective of this work is to study the performances of massively parallel 32 SIMD on-chip architectures with current design methodologies based on recent integration technologies.…”