Soft-defect detection (SDD) technique for a high-reliability CMOS SRAM

Kuo, C.; Toms, T.; Neel, B.T.; Jelemensky, J.; Carter, E.A.; Smith, Philip H.

doi:10.1109/4.50285

Cited by 27 publications

(10 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A technique known as soft-defect detection (SDD), accomplished at room temperature was described by Kuo et al in [14]-this provides a complete data retention test of a CMOS SRAM array. The SDD technique has two components-an open circuit test that checks for connectivity of the p-type load transistor, and a cell-array test that carefully monitors the standby array current to detect abnormally high current leakage.…”

Section: Testing For Static Data Lossmentioning

confidence: 99%

“…To make IDDQ testing faster, the soft-defect-detection approach [14], described earlier, used the concept of builtin current monitors for fast current sensing.…”

Section: Testing Of Srams By Monitoring Idd the Dynamic Power Supplymentioning

confidence: 99%

“…Variations in process parameters are seen to result in delay faults. Another peculiar fact observed in GaAs SRAMs is that data retention faults have an entirely new mechanism, apart from the stuck-open mechanism observed in silicon [7,14]. Parametric test procedures for these faults are described shortly.…”

Section: Faults In Gallium Arsenide (Gaas) Srams and Their Testingmentioning

confidence: 99%

See 2 more Smart Citations

Technology and layout-related testing of static random-access memories

Chakraborty

Mazumder

1994

J Electron Test

View full text Add to dashboard Cite

Abstract. Static random-access memories (SRAMs) exhibit faults that are electrical in nature. Functional and electrical testing are performed to diagnose faulty operation. These tests are usually designed from simple fault models that describe the chip interface behavior without a thorough analysis of the chip layout and technology. However, there are certain technology and layout-related defects that are internal to the chip and are mostly time-dependent in nature. The resulting failures may or may not seriously degrade the input/output interface behavior. They may show up as electrical faults (such as a slow access fault) and/or functional faults (such as a pattern sensitive fault). However, these faults cannot be described properly with the functional fault models because these models do not take timing into account. Also, electrical fault models that describe merely the input/output interface behavior are inadequate to characterize every possible defect in the basic SRAM cell. Examples of faults produced by these defects are: (a) static data loss, (b) abnormally high currents drawn from the power supply, etc. Generating tests for such faults often requires a thorough understanding and analysis of the circuit technology and layout. In this article, we shall examine ways to characterize and test such faults. We shall divide such faults into two categories depending on the types of SRAMs they effect-silicon SRAMs and GaAs SRAMs.

show abstract

Section: Testing For Static Data Lossmentioning

confidence: 99%

“…To make IDDQ testing faster, the soft-defect-detection approach [14], described earlier, used the concept of builtin current monitors for fast current sensing.…”

Section: Testing Of Srams By Monitoring Idd the Dynamic Power Supplymentioning

confidence: 99%

Section: Faults In Gallium Arsenide (Gaas) Srams and Their Testingmentioning

confidence: 99%

See 1 more Smart Citation

Technology and layout-related testing of static random-access memories

Chakraborty

Mazumder

1994

J Electron Test

View full text Add to dashboard Cite

show abstract

“…When the resistance is large there is a data retention problem. It may be noted tbat this problem occurs even though there is no missing pull-up-the chief cause of data retention problems in silicon SRAM's [ 111, [20].…”

Section: Analysis Of Resistive/leakage Current Failure Modesmentioning

confidence: 99%

Analytical and simulation studies of failure modes in SRAMs using high electron mobility transistors

Mohan

Mazumder

1993

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-Gallium Arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper studies the behavior of Gallium Arsenide High Electron Mobility Transistor (HEMT) memories in the presence of material defects, processing errors and design errors to formulate efficient testing schemes. All defects and errors are mapped into equivalent circuit modifications and the resulting circuits are analyzed and simulated to observe the fault effects. Certain complex pattern-sensitive faults described in the testing literature are not observed at all, while certain other faults which have not been previously studied, are observed. It is shown that by slightly modifying and reordering existing test procedures, all faults in these RAM'S can be adequately tested.

show abstract

“…Conversely, an elevated word line voltage that further degrades the stored "zero" level and thus reduces the cell's SNM can be used to apply the test stress and detect a weak cell [15]. Kuo et al [16] suggested a Soft Defect Detection (SDD) technique based on the fact that defect-free inverters of an SRAM cell will provide certain I read upon access. If there is a open in a cell's connections, the I read may be insufficient or absent.…”

Section: Single Test Stressmentioning

confidence: 99%

Word line pulsing technique for stability fault detection in sram cells

Pavlov

Azimane

Gyvez

et al.

IEEE International Conference on Test, 2005.

View full text Add to dashboard Cite

Pavlov, A.; Azimane, M.; Pineda de Gyvez, J.; Sachdev, M. Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim.

show abstract

Soft-defect detection (SDD) technique for a high-reliability CMOS SRAM

Cited by 27 publications

References 6 publications

Technology and layout-related testing of static random-access memories

Technology and layout-related testing of static random-access memories

Analytical and simulation studies of failure modes in SRAMs using high electron mobility transistors

Word line pulsing technique for stability fault detection in sram cells

Contact Info

Product

Resources

About