Soft Error Reliability Improvement of Digital Circuits by Exploiting a Fast Gate Sizing Scheme

Raji, Mohsen; Sabet, M. Amin; Ghavami, Behnam

doi:10.1109/access.2019.2902505

Cited by 16 publications

(8 citation statements)

References 37 publications

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“…For both LET values, the circuits with higher drive strength (X2) have shown lower cross-section, as expected [34]. A common hardening technique is to upsize transistor dimensions to increase the nodal capacitance of the circuit and, consequently, the critical charge needed to observe a SET [34][35][36][37]. For 78 MeV•cm 2 /mg, the INV_X2, NAND_X1, and NAND_X2 provide the lowest SET cross-sections from all analyzed cells.…”

Section: Set Immunity Of Standard-cell Logic Gatessupporting

confidence: 55%

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

et al. 2020

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Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects. However, the importance of considering SET in Very-Large-System-Integration (VLSI) circuits increases given the reduction of the transistor dimensions and the logic data path depth in advanced technology nodes. Accordingly, the threat of SET in electronics systems for space applications must be carefully addressed along with the SEU characterization. In this work, a systematic prediction methodology to assess and improve the SET immunity of digital circuits is presented. Further, the applicability to full-custom and cell-based design methodologies are discussed, and an analysis based on signal probability and pin assignment is proposed to achieve a more application-efficient SET-aware optimization of synthesized circuits. For instance, a SET-aware pin assignment can provide a reduction of 37% and 16% on the SET rate of a NOR gate for a Geostationary Orbit (GEO) and the International Space Station (ISS) orbit, respectively.

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Section: Set Immunity Of Standard-cell Logic Gatessupporting

confidence: 55%

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

et al. 2020

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“…The graph in Figure 2b depicts how the time duration value decreased as the energy increased which is similar to Figure 3a that depicts how the peak drain current decreased with the incident energy. Therefore, there is a correlation between the amount of EHP generated by alpha particle incidence, which affects the peak drain current according to alpha particle incidence [35][36][37][38][39]. Figure 4 shows peak drain current with different doping concentration when the source was fixed to 1 × 10 20 cm −3 and the doping concentration of the channel was set to 1 × 10 16 and 1 × 10 17 cm −3 .…”

Section: Three-dimensional (3d) Device and Methodologymentioning

confidence: 99%

Alpha Particle Effect on Multi-Nanosheet Tunneling Field-Effect Transistor at 3-nm Technology Node

et al. 2019

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The radiation effects on a multi-nanosheet tunneling-based field effect transistor (NS-TFET) were investigated for a 3-nm technology node using a three-dimensional (3D) technology computer-aided design (TCAD) simulator. An alpha particle was injected into a field effect transistor (FET), which resulted in a drain current fluctuation and caused the integrated circuit to malfunction as the result of a soft-error-rate (SER) issue. It was subsequently observed that radiation effects on NS-TFET were completely different from a conventional drift-diffusion (DD)-based FET. Unlike a conventional DD-based FET, when an alpha particle enters the source and channel areas in the current scenario, a larger drain current fluctuation occurs due to a tunneling mechanism between the source and the channel, and this has a significant effect on the drain current. In addition, as the temperature increases, the radiation effect increases as a result of a decrease in silicon bandgap energy and a resultant increase in band-to-band generation. Finally, the radiation effect was analyzed according to the energy of the alpha particle. These results can provide a guideline by which to design a robust integrated circuit for radiation that is totally different from the conventional DD-FET approach.

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“…Because of the nanoscales used in the manufacturing of semiconductors, the increase in the number of malicious faults, such as event upsets, is inevitable in the existing integrated chips [8,9]. To mitigate this problem, these faults should be carefully dealt with, beginning from the design stage to the manufacturing stage.…”

Section: Fault-tolerant Techniquesmentioning

confidence: 99%

“…As the manufacturing technology for semiconductors continues to scale down, designing high-performance hardware with a smaller size, high throughput, and low power consumption has become an easy task for circuit designers. However, the probability of the occurrence of unexpected faults inevitably increases in integrated circuits [8,9]. Because it is impossible to eliminate unexpected faults completely, the faults should be carefully considered, beginning with the design stage to the manufacturing stage [10].…”

Section: Introductionmentioning

confidence: 99%

Area-Efficient Differential Fault Tolerance Encoding for Finite State Machines

Park

Yoo

2020

Electronics

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A differential fault tolerance encoding is presented for finite state machines (FSMs) to improve their area efficiency. As the manufacturing technology for semiconductors continues to scale down, the probability of the occurrence of unexpected faults in integrated circuits has been increasing. Because an FSM controls an entire digital circuit, the faults in FSMs should be carefully addressed. Whereas the previous encoding applies a fault tolerance scheme to all the states in an FSM, the proposed encoding applies a fault tolerance scheme to only specific states depending on their importance. Compared with the previous complete fault tolerance encoding, the proposed encoding provides a comparable failure probability with a small hardware by applying the fault tolerance scheme differently to each state. The proposed method improves the area efficiency by 36.1%, 43.8%, 49.2%, and 74.6% compared with that by the non-fault tolerance, previous hardware redundancy, information redundancy, and time redundancy methods, respectively. Consequently, the proposed method can provide a flexible solution by applying the fault tolerance differently depending on the importance of the states.

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Soft Error Reliability Improvement of Digital Circuits by Exploiting a Fast Gate Sizing Scheme

Cited by 16 publications

References 37 publications

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

Alpha Particle Effect on Multi-Nanosheet Tunneling Field-Effect Transistor at 3-nm Technology Node

Area-Efficient Differential Fault Tolerance Encoding for Finite State Machines

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