Soft-type trap-induced degradation of MoS₂ field effect transistors

Abstract

The practical applicability of electronic devices is largely determined by the reliability of field effect transistors (FETs), necessitating constant searches for new and better-performing semiconductors. We investigated the stress-induced degradation of MoS multilayer FETs, revealing a steady decrease of drain current by 56% from the initial value after 30 min. The drain current recovers to the initial state when the transistor is completely turned off, indicating the roles of soft-traps in the apparent degradation. The noise current power spectrum follows the model of carrier number fluctuation-correlated mobility fluctuation (CNF-CMF) regardless of stress time. However, the reduction of the drain current was well fitted to the increase of the trap density based on the CNF-CMF model, attributing the presence of the soft-type traps of dielectric oxides to the degradation of the MoS FETs.

Multiple machine learning approach to characterize two-dimensional nanoelectronic devices via featurization of charge fluctuation

“…We employ this data processing algorithm for a number of ΔI(t) data obtained from various 2D material based FETs which have been fabricated and analyzed under various experimental conditions such as different gate dielectrics 11,13,34,35 , temperatures 11,34,36 , channel materials 10,11,13,34,35,[37][38][39] , chemical/electron beam doping 40,41 , and source/drain contact metals 11,34 (see Fig. 1b).…”

Metal-Contact Improvement in a Multilayer WSe2 Transistor through Strong Hot Carrier Injection

“…Schottky barriers inevitably form at the semiconductor TMD–metal junctions, which can greatly degrade device performance . The Schottky barriers are not simply determined by the difference between the conduction band minimum or the valance band maximum of the TMD and the work function of the metal, but forming an Ohmic contact is difficult because Fermi level pinning occurs. − Research studies on the interface between the TMD and the metal and the interface between the TMD and the gate dielectric have been actively performed. − Recently, studies have been conducted to improve the interface property by inserting a dangling bond-free hexagonal BN ( h -BN) between the TMD and the gate dielectric − or between the TMD and the metal contact . In addition, some studies have shown that thermal annealing alleviated Fermi level pinning by improving interfacial properties. ,,,, …”