Software Code Generation for the RVC-CAL Language

Wipliez, Matthieu; Roquier, Ghislain; Nezan, Jean-François

doi:10.1007/s11265-009-0390-z

Cited by 70 publications

(63 citation statements)

References 12 publications

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“…Actors have since then become widely used [1][2][3][4][36][37][38][39][40][41], especially in embedded systems, where actor-oriented design is a natural match to the heterogeneous and concurrent nature of such systems.…”

Section: Actor-based Dataflow Modelingmentioning

confidence: 99%

Pipeline synthesis and optimization of FPGA-based video processing applications with CAL

Rahman

Prihozhy

Mattavelli

2011

J Image Video Proc.

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This article describes a pipeline synthesis and optimization technique that increases data throughput of FPGAbased system using minimum pipeline resources. The technique is applied on CAL dataflow language, and designed based on relations, matrices, and graphs. First, the initial as-soon-as-possible (ASAP) and as-late-aspossible (ALAP) schedules, and the corresponding mobility of operators are generated. From this, operator coloring technique is used on conflict and nonconflict directed graphs using recursive functions and explicit stack mechanisms. For each feasible number of pipeline stages, a pipeline schedule with minimum total register width is taken as an optimal coloring, which is then automatically transformed to a description in CAL. The generated pipelined CAL descriptions are finally synthesized to hardware description languages for FPGA implementation. Experimental results of three video processing applications demonstrate up to 3.9× higher throughput for pipelined compared to non-pipelined implementations, and average total pipeline register width reduction of up to 39.6 and 49.9% between the optimal, and ASAP and ALAP pipeline schedules, respectively.

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Section: Actor-based Dataflow Modelingmentioning

confidence: 99%

Pipeline synthesis and optimization of FPGA-based video processing applications with CAL

Rahman

Prihozhy

Mattavelli

2011

J Image Video Proc.

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“…The Open RVC-CAL Compiler (Orcc) 1 is an open-source framework designed to generate implementation code from a network of RVC-CAL actors specified by a network topology description [15].…”

Section: Open Rvc-cal Compilermentioning

confidence: 99%

A unified hardware/software co-synthesis solution for signal processing systems

Bezati

Yviquel

Raulet

et al. 2011

Proceedings of the 2011 Conference on Design &Amp; Architectures for Signal &Amp; Image Processing (DASIP)

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This paper presents a methodology to specify from a highlevel data-flow description an application for both hardware and software synthesis. Firstly, an introduction to RVC-CAL data-flow programming and Orcc framework is presented. Furthermore, an analysis of a close to gate intermediate representation (XLIM) is bestowed. As a proof of concept a JPEG codec was written purely in RVC-CAL to test the co-synthesis tools and then an analysis of the generated hardware and software results are given. Our experience shows that using RVC-CAL can unify the process of creating the same application for software and hardware without modifying a single source code for each solution.

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“…We further modified the scheduler of CAL2C to better accommodate SSRs [3]. All of the SystemC primitives have been removed from the current version of Cal2C.…”

Section: E Concurrency Analysis Of the Mpeg-4 Sp Decodermentioning

confidence: 99%

“…References [1], [3], [4] cover related aspects of reconfigurable video coding and CAL-oriented tools. In particular, [1] gives an overview of the overall RVC framework; Reference [3] provides details on the software code generator CAL2C; and Reference [4] elaborates on a hardware code generator for CAL.…”

Section: Introductionmentioning

confidence: 99%

“…In particular, [1] gives an overview of the overall RVC framework; Reference [3] provides details on the software code generator CAL2C; and Reference [4] elaborates on a hardware code generator for CAL. In contrast, this paper is distinctive in it focus on analyzing concurrency and exploiting parallelism; the topic of concurrency is not addressed in depth in References [1], [3] and [4].…”

Section: Introductionmentioning

confidence: 99%

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Exploring the Concurrency of an MPEG RVC Decoder Based on Dataflow Program Analysis

Janneck

Bhattacharyya

et al. 2009

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-This paper presents an in-depth case study on dataflow-based analysis and exploitation of parallelism in the design and implementation of an MPEG RVC (reconfigurable video coding) decoder. Dataflow descriptions have been used in a wide range of digital signal processing (DSP) applications, such as applications for multimedia processing and wireless communications. Because dataflow models are effective in exposing concurrency and other important forms of high level application structure, dataflow techniques are promising for implementing complex DSP applications on multi-core systems, and other kinds of parallel processing platforms. In this paper, we use the CAL language as a concrete framework for representing and demonstrating dataflow design techniques.Furthermore, we also describe our application of The DIF package (TDP), a software tool for analyzing dataflow networks, to the systematic exploitation of concurrency in CAL networks that are targeted to multi-core platforms. Using TDP, one is able to automatically process regions that are extracted from the original network, and exhibit properties similar to synchronous dataflow (SDF) models. This is important in our context because powerful techniques, based on static scheduling, are available for exploiting concurrency in SDF descriptions. Detection of SDFlike regions is an important step for applying static scheduling techniques within a dynamic dataflow framework. Furthermore, segmenting a system into SDF-like regions also allows us to explore cross-actor concurrency that results from dynamic dependencies among different regions. Using SDF-like region detection as a preprocessing step to software synthesis generally provides an efficient way for mapping tasks to multi-core systems, and improves the system performance of video processing applications on multi-core platforms.

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Software Code Generation for the RVC-CAL Language

Cited by 70 publications

References 12 publications

Pipeline synthesis and optimization of FPGA-based video processing applications with CAL

Pipeline synthesis and optimization of FPGA-based video processing applications with CAL

A unified hardware/software co-synthesis solution for signal processing systems

Exploring the Concurrency of an MPEG RVC Decoder Based on Dataflow Program Analysis

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