Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors

Schöne, Robert; Ilsche, Thomas; Bielert, Mario; Molka, Daniel; Hackenberg, Daniel

doi:10.1109/e2sc.2016.015

Cited by 15 publications

(10 citation statements)

References 5 publications

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“…Likewise, we also show in [6] how long it takes to enter an idle state. Finally, we describe the effect of clock modulation (throttling) in [7]. This paper covers P-state and C-state transitions in Section V and Section VI, respectively.…”

Section: Related Work On Efficiency Mechanisms a Acpi Statesmentioning

confidence: 99%

“…To support the decision of the OS, which C-state to use, processors typically hand over ACPI objects describing the transition latency and the average power consumption [3, Section 8.4.2.1]. On our test system, three C-states are supported, the active C-state C0, and two additional idling C-states, C1 and C2 7 . While the former is entered with the instructions monitor and mwait, the latter uses IO address 0x814 in the C-state address range described in Section III-B.…”

Section: Power State Detailsmentioning

confidence: 99%

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Energy Efficiency Aspects of the AMD Zen 2 Architecture

Schöne,

Ilsche,

Bielert

et al. 2021

Preprint

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In High Performance Computing, systems are evaluated based on their computational throughput. However, performance in contemporary server processors is primarily limited by power and thermal constraints. Ensuring operation within a given power envelope requires a wide range of sophisticated control mechanisms. While some of these are handled transparently by hardware control loops, others are controlled by the operating system. A lack of publicly disclosed implementation details further complicates this topic. However, understanding these mechanisms is a prerequisite for any effort to exploit the full computing capability and to minimize the energy consumption of today's server systems. This paper highlights the various energy efficiency aspects of the AMD Zen 2 microarchitecture to facilitate system understanding and optimization. Key findings include qualitative and quantitative descriptions regarding core frequency transition delays, workload-based frequency limitations, effects of I/O die P-states on memory performance as well as discussion on the built-in power monitoring capabilities and its limitations. Moreover, we present specifics and caveats of idle states, wakeup times as well as the impact of idling and inactive hardware threads and cores on the performance of active resources such as other cores.

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Section: Related Work On Efficiency Mechanisms a Acpi Statesmentioning

confidence: 99%

Section: Power State Detailsmentioning

confidence: 99%

Energy Efficiency Aspects of the AMD Zen 2 Architecture

Schöne,

Ilsche,

Bielert

et al. 2021

Preprint

Self Cite

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“…In addition to DVFS, Intel processors support duty cycle modulation (Schöne et al, 2016) that “squashes” CPU clock without changing the real frequency for each individual core. Zhang et al (2009) use duty cycling to efficiently manage on-chip shared resources.…”

Section: Related Workmentioning

confidence: 99%

Performance and energy analysis of OpenMP runtime systems with dense linear algebra algorithms

Lima

Raïs

Lefèvre

et al. 2018

The International Journal of High Performance Computing Applica

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In this paper, we analyse performance and energy consumption of five OpenMP runtime systems over a NUMA platform. We also selected three CPU level optimizations, or techniques, to evaluate their impact on the runtime systems: processors features Turbo Boost and C-States, and CPU DVFS through Linux CPUFreq governors. We present an experimental study to characterize OpenMP runtime systems on the three main kernels in dense linear algebra algorithms (Cholesky, LU and QR) in terms of performance and energy consumption. Our experimental results suggest that OpenMP runtime systems can be considered as a new energy leverage, and Turbo Boost, as well as C-States, impacted significantly performance and energy. CPUFreq governors had more impact with Turbo Boost disabled, since both optimizations reduced performance due to CPU thermal limits. A LU factorization with concurrent write extension from libKOMP achieved up to 63% of performance gain and 29% of energy decrease.

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“…In the case of multicore processors, per-core DVFS is not yet widely supported (Intel Haswell-EP and Samsung Exynos processors are known to support it). However, many recent studies have shown the benefits of per-core or per-cluser-ofcores DVFS capabilities [4], [5], [6], [7], [8], [9] . Our work is under the assumption that such per-core DVFS may be possible in the future multicore processors and it is under this assumption that we implement and test the proposed ideas inside the Sniper system simulator.…”

Section: Introductionmentioning

confidence: 99%

Dynamic energy management for chip multi-processors under performance constraints

Moghaddam

Ababei

2017

Microprocessors and Microsystems

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We introduce a novel algorithm for dynamic energy management (DEM) under performance constraints in chip multi-processors (CMPs). Using the novel concept of delayed instructions count, performance loss estimations are calculated at the end of each control period for each core. In addition, a Kalman filtering based approach is employed to predict workload in the next control period for which voltage-frequency pairs must be selected. This selection is done with a novel dynamic voltage and frequency scaling (DVFS) algorithm whose objective is to reduce energy consumption but without degrading performance beyond the user set threshold. Using our customized Sniper based CMP system simulation framework, we demonstrate the effectiveness of the proposed algorithm for a variety of benchmarks for 16 core and 64 core network-on-chip based CMP architectures. Simulation results show consistent energy savings across the board. We present our work as an investigation of the tradeoff between the achievable energy reduction via DVFS when predictions are done using the effective Kalman filter for different performance penalty thresholds.

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Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors

Cited by 15 publications

References 5 publications

Energy Efficiency Aspects of the AMD Zen 2 Architecture

Energy Efficiency Aspects of the AMD Zen 2 Architecture

Performance and energy analysis of OpenMP runtime systems with dense linear algebra algorithms

Dynamic energy management for chip multi-processors under performance constraints

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