Software in a hardware view: New models for HW-dependent software in SoC verification and test

Villarraga, Carlos; Schmidt, Bernard; Bao, Binghao; Raman, Rakesh; Bartsch, Christian; Fehmel, Thomas; Stoffel, Dominik; Kunz, Wolfgang

doi:10.1109/test.2014.7035308

Cited by 9 publications

(4 citation statements)

References 18 publications

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“…On the other hand, semi-formal verification techniques through the use of formalisms applied in conjunction with simulation have proved to be reasonably efficient in this respect. Several approaches have dealt with failure in device drivers by performing formal or semi-formal verification during the development phase [12][13][14][15][16][17][18][19][20].…”

Section: Related Workmentioning

confidence: 99%

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Towards a greater reliability of driver/device communication around the system life cycle through a contract‐based protocol specification

Macieira

Barros

2017

IET cyber-phys. syst.

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Section: Related Workmentioning

confidence: 99%

“…1, pp. [11][12][13][14][15][16][17][18][19][20][21][22][23] This is an open access article published by the IET under the Creative Commons Attribution-NonCommercial-NoDerivs License (http://creativecommons.org/licenses/by-nc-nd/3.0/) further challenge is revealed, since it is necessary to verify the two domains together.…”

Section: Introductionmentioning

confidence: 99%

Towards a greater reliability of driver/device communication around the system life cycle through a contract‐based protocol specification

Macieira

Barros

2017

IET cyber-phys. syst.

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“…Some academic works [20,23,26,27,28,30,31] have tried to achieve unified verification of hardware and software for specific designs. For instance, in [23], Kroening et al propose a methodology for formally verifying a mixed hardware/software design implemented in SystemC.…”

Section: Related Workmentioning

confidence: 99%

SMASHUP: a toolchain for unified verification of hardware/software co-designs

Lugou¹,

Apvrille²,

Francillon³

2016

J Cryptogr Eng

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Critical and privacy-sensitive applications of smart and connected objects such as health-related objects are now common, thus raising the need to design these objects with strong security guarantees. Many recent works offer practical hardware-assisted security solutions that take advantage of a tight cooperation between hardware and software to provide system-level security guarantees. Formally and consistently proving the efficiency of these solutions raises challenges since software and hardware verifications approaches generally rely on different representations. The paper first sketches an ideal security verification solution naturally handling both hardware and software components. Next, it proposes an evaluation of formal verification methods that have already been proposed for mixed hardware/software systems, with regards to the ideal method. At last, the paper presents a conceptual approach to this ideal method relying on ProVerif, and applies this approach to a remote attestation system (SMART).

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“…The proposed method, however, is easily adaptable for time-accurate instruction cells that can be created for processors with predictable execution times. In [16] a time-accurate version of an instruction cell called timed instruction cell was introduced for this purpose. In the case a single hardware fault has an effect on multiple processor instructions, the effects can be modeled by creating a corresponding fault description for every affected instruction cell.…”

Section: Fault Descriptionmentioning

confidence: 99%

A HW-dependent software model for cross-layer fault analysis in embedded systems

Bartsch

Rödel

Villarraga

et al. 2016

2016 17th Latin-American Test Symposium (LATS)

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Abstract. With the advent of new microelectronic fabrication technologies new hardware devices are emerging which suffer from an intrinsically higher susceptibility to faults than previous devices. This leads to a substantially lower degree of reliability and demands further improvements of error detection methods. However, any attempt to cover all errors for all theoretically possible scenarios that a system might be used in can easily lead to excessive costs. Instead, an application-dependent approach should be taken, i.e., strategies for test and error resilience must target only those errors that can actually have an effect in the situations in which the hardware is being used.In this paper, we propose a method to inject faults into hardware and to formally analyze their effects on the software behavior. We describe how this analysis can be implemented based on a recently proposed hardware-dependent software model called program netlist. We show how program netlists can be extended to formally model the behavior of a program in the event of one or more hardware faults. First experimental results are presented to demonstrate the feasibility of our approach.

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Software in a hardware view: New models for HW-dependent software in SoC verification and test

Cited by 9 publications

References 18 publications

Towards a greater reliability of driver/device communication around the system life cycle through a contract‐based protocol specification

Towards a greater reliability of driver/device communication around the system life cycle through a contract‐based protocol specification

SMASHUP: a toolchain for unified verification of hardware/software co-designs

A HW-dependent software model for cross-layer fault analysis in embedded systems

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