SOI CMOS with high-performance passive components for analog, RF, and mixed signal design

Stuber, M.; Megahed, M.; Lee, J.J.; Kobayashi, T.; Domyo, H.

doi:10.1109/soi.1998.723130

Cited by 11 publications

(6 citation statements)

References 4 publications

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“…Other, more exotic bulk approaches to improving substrate resistivity or isolation have also been proposed for RF-SOC applications. These include the use of silicon-on-insulator (SOI) [10], silicon-on-sapphire (SOS) [11], silicon-on-anything (SOA) [12], porous silicon [13], through substrate vias [14], and bulk micromachining [15]. None of these techniques have found their way into widespread use, although there have been some notable successes in niche applications.…”

Section: Substrate and Isolation Technologies For Rf-soc Applicatmentioning

confidence: 99%

Silicon technology tradeoffs for radio-frequency/mixed-signal "systems-on-a-chip"

Larson¹

2003

IEEE Trans. Electron Devices

100

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Silicon technology has progressed over the last several years from a digitally oriented technology to one well suited for microwave and RF applications at a high level of integration. Technology scaling, both at the transistor and back-end metallization level, has driven this progress. CMOS technology is ideally suited for low-noise amplification and receiver applications, but the fundamental breakdown voltage is lower than that of equivalent Si/SiGe HBTs. High-quality passive devices are equally important, and improvements in metallization technology are resulting in higher quality inductors. This paper summarizes the silicon technology issues associated with RF "system-on-a-chip" applications.

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Section: Substrate and Isolation Technologies For Rf-soc Applicatmentioning

confidence: 99%

Silicon technology tradeoffs for radio-frequency/mixed-signal "systems-on-a-chip"

Larson¹

2003

IEEE Trans. Electron Devices

100

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“…Advantages of SOI CMOS technology over bulk CMOS are mainly due to deep-submicron devices with low parasitics and high-Q passive components. RFIC designers have recently shown interest in the SOI CMOS for low-power and high-speed applications [3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

UHF RF Front-End Circuits in 0.35-μm Silicon on Insulator (SOI) CMOS

Zencir

Huang

Tekin

et al. 2005

Analog Integr Circ Sig Process

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In this work, design and measurement results of UHF RF frontend circuits to be used in low-IF and subsampling receiver architectures are presented. We report on three low noise amplifiers (LNA) (i) single-ended (ii) differential (iii) high-gain differential and a double-balanced mixer all implemented in 0.35-µm SOI (Silicon on Insulator) CMOS technology of Honeywell. These circuits are considered as candidate low-power building blocks to be used in the two fully-integrated receiver chips targeted for deep space communications. Characteristics of square spiral inductors with high quality (Q) factors (as high as 10.8) in SOI CMOS are reported. Single-ended and fully-differential LNA's provide gains of 17.5 dB and 18.74 dB at 435 MHz, respectively. Noise figure of the single-ended LNA is 2.91 dB while the differential LNA's noise figure is 3.25 dB. These results were obtained for the power dissipations of 12.5 mW and 16.5 mW from a 2.5-V supply for the single-ended and differential LNA's, respectively. High-gain low-power differential LNA provides a small-signal gain of 45.6 dB with a noise figure of 2.4 dB at 435 MHz. Total power dissipation of the high gain LNA is 28 mW from a 3.3-V supply. The double-balanced mixer provides a conversion gain of 5.5 dB with a noise figure of 13 dB at 2 MHz IF. The power dissipation of the mixer is 11.5 mW from a 2.5-V supply. The measured responses and the power dissipations of the building blocks meet the requirements of the communications system. The die areas occupied by the single-ended LNA, differential LNA, high-gain LNA and the mixer are 0.6 mm × 1.4 mm, 1 mm × 1.4 mm, 1.4 mm × 1.2 mm and 0.6 mm × 0.9 mm, respectively.

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“…One type of enhancement that has attracted considerable interest for power electronics devices and signal-level RF transistors is silicon-on-insulator (SOI) substrates [6][7][8][9]. In this technology a buried dielectric (BOX) layer is inserted between the transistor and the bottom surface of the semiconductor die.…”

Section: Introductionmentioning

confidence: 99%

“…The inherent advantages of SOI (reduced capacitance and better thermal ruggedness) are highly desirable characteristics for RF power amplifiers. Moreover, the utility of SOI as a platform for monolithic integration of signal-level VLSI electronics and passive components suggests that SOI will be the leading technology for integrated power amplifiers [8,9,13].…”

Section: Introductionmentioning

confidence: 99%

Low Energy / Low Noise Electrical Component for Mobile Platform Applications

Shenai¹,

Leong²

2000

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SOI CMOS with high-performance passive components for analog, RF, and mixed signal design

Cited by 11 publications

References 4 publications

Silicon technology tradeoffs for radio-frequency/mixed-signal "systems-on-a-chip"

Silicon technology tradeoffs for radio-frequency/mixed-signal "systems-on-a-chip"

UHF RF Front-End Circuits in 0.35-μm Silicon on Insulator (SOI) CMOS

Low Energy / Low Noise Electrical Component for Mobile Platform Applications

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