SOI FinFET Based 10T SRAM Cell Design against Short Channel Effects

Abstract

Continuous scaling of CMOS devices makes the density of Static Random Access memory (SRAM) array size increases. Maintaining high yield in SRAMs becomes more difficult at lower technology nodes, since they are unguarded to the process variations due to the large array size and cell miniaturization, this factor motivates towards the investigation of new techniques and technologies. FinFET technology is the promising technology with which all hurdles of CMOS technology can be overcome. In this paper, a novel 10T SRAM cell has been proposed, and is designed with both CMOS and FinFET technologies and finally the comparisons are made to know the better one. Synopsis TCAD and Cadence Virtuoso tools has been used to carry out SRAM designs.

Soft-Error Reduction and Enhancement of Write Stability and Hold Power Optimization by using 12T SRAM for Aerospace Applications

“…The literature survey in Ch Santhi Rani, D Sudha, Sreenivasa Rao Ijjada [3] comparing the proposed 10T SRAM cell design in both CMOS and Fin FET technologies with existing cell designs in the literature to showcase its advantages in terms of stability and power consumption.Wing-Hung Ki and Chi-Ying Tsui [1] SARP12T is immune to SEUs of both polarities induced at any sensitive node and can recover from SEMNUs that occur at its storage node-pair also consumes the lowest hold power dominance among all the cells under consideration. Ch Santhi Rani, D Sudha, Sreenivasa Rao [2] summarizes the importance of semiconductor memories, the challenges in bulk CMOS scaling, and the advantages of using Fin FET technology as an alternative.…”