Solving the State Assignment Problem Using Stochastic Search Aided with Simulated Annealing

Aly, Walid Mohamed

doi:10.3844/ajeassp.2009.703.707

Cited by 12 publications

(5 citation statements)

References 8 publications

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“…Figure 2 shows a multi-level/stage inventory system, system with connected set of stages representing the steps for assembly and/or distribution for a family of products. The general product structure can be split into the following 4 special cases namely the assembly; serial; parallel and single stage multi-item (Aly, 2009;Vijay and Manoharan, 2010). (Discussion on these cases will not be given in this study).…”

Section: Methodsmentioning

confidence: 99%

Modeling of Multi-Level Capacitated Lot-Size Scheduling Problem

Ismail¹,

Mahad

Ching

2011

American Journal of Applied Sciences

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Problem statement: Lot-size is the clustering of items for transportation or manufacturing processes occurring at the same time. The issue in lot-size problem is to design production processes so that the feasible production quantities are equal to customer demand quantities and the timing of production is such that inventory positions are almost zero. Approach: In this study, we explore the multi-level lot-size and scheduling problem. It is on a multi-level capacitated lot-size problem or known as the multi-level lot-size problem with bottlenecks. Two models were introduced to solve the multi-level lot-size problem namely the Billington model and Alf Kimms model. Using these models, a simple heuristic method was designed to solve a multi level capacitated lot sizing scheduling problem. Results: In this study, we showed that Alf Kimms model is more efficient than Billington model. The result given by Alf Kimms model is always feasible without further modification unlike the Billington model. This is due to the way the constraint is devised to ensure the inventory balance. The constraint used in Alf Kimms model ensures that inventory in hand is always sufficient to fulfill the demand occurred in each period. However, the use of this constraint in Billington model is to ensure that the total production for each item is always greater than or equal to the total external demand in the time horizon. Therefore, without some form of modification, the result given by Billington model will be infeasible production plan. Conclusion: A comparative study between these models shows that both models were successfully devised to solve capacitated multi-level lot sizing problem with the objective function to minimize the total holding costs and setup- cost. This study also shows that the production schedule will always start at the last period because this will give the lowest costs and it also shows that Alf Kimms model gives a set of feasible sub-optimal schedule compare to Billington model

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Section: Methodsmentioning

confidence: 99%

Modeling of Multi-Level Capacitated Lot-Size Scheduling Problem

Ismail¹,

Mahad

Ching

2011

American Journal of Applied Sciences

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“…Some algorithms are based on simulated annealing for optimizing area and/or power. In [128], the approximate fitness function is used to optimize the area. In [129], both area and power are optimized.…”

Section: Saving Power By State Assignmentmentioning

confidence: 99%

Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review

Barkalov,

Titarenko,

Bieganowski

et al. 2024

Applied Sciences

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Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. The review outlines the main approaches to solving this problem that have been developed over the last 40 years. The main sources of power dissipation in CMOS circuits are shown; the static and dynamic components of this phenomenon are analyzed. The power consumption saving can be achieved by using coarse-grained methods common to all digital systems. These methods are based on voltage or/and clock frequency scaling. The review shows the main structural diagrams generated by the use of these methods when optimizing the power characteristics of FSM circuits. Also, there are various known fine-grained methods taking into account the specifics of both FSMs and logic elements used. Three groups of the fine-grained methods targeting FPGA-based FSM circuits are analyzed. These groups include clock gating, state assignment, and replacing look-up table (LUT) elements by embedded memory blocks (EMBs). The clock gating involves a separate or joint use of such approaches as the (1) decomposition of FSM inputs and (2) disabling FSM inputs. The aim of the power-saving state assignment is to reduce the switching activity of a resulting FSM circuit. The replacement of LUTs by EMBs allows a reduction in the power consumption due to a decrease in the number of FSM circuit elements and their interconnections. We hope that the review will help experts to use known methods and develop new ones for reducing power consumption. We think that a good knowledge and understanding of existing methods of reducing power consumption is a prerequisite for the development of new, more effective methods to solve this very important problem. Although the methods considered are mainly aimed at FPGA-based FSMs, they can be modified, if necessary, and used for the power consumption optimization of FSM circuits implemented with other logic elements.

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“…In addition to encode the states, the proposed technique assigns values to the don't care outputs to achieve its objective. There is a key difference between the proposed technique and the conventional state-encoding approaches [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20] that justifies its novelty. State-encoding algorithms assign a different code to each FSM state with the purpose of simplifying the complexity of the transition and output functions.…”

Section: Mapping Outputs and States Encoding Bits To Outputs By Means...mentioning

confidence: 99%

“…Constraints ( 11) and ( 12) ensure that the state-encoding bits and the outputs, respectively, are not mapped more than once (see Figure 3a,b). Constraint (13) guarantees that any output cannot be used to generate more than one signal by means of a multiplexer, whether a state-encoding bit or an output (see Figure 3c). Constraints ( 14) and (15) prevent that an output is mapped to itself (see Figure 3d).…”

Section: Integer Linear Programming Formulationmentioning

confidence: 99%

“…For this reason, the synthesis of FSMs has received the attention of researchers, designers and EDA tool developers for decades [1][2][3][4]. One of the most active fields has been the encoding of the FSM states to achieve optimal implementations of the state transition and output functions [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

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Mapping Outputs and States Encoding Bits to Outputs Using Multiplexers in Finite State Machine Implementations

Senhadji-Navarro

García-Vargas²

2023

Electronics

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This paper proposes a new technique for implementing Finite State Machines (FSMs) in Field Programmable Gate Arrays (FPGAs). The proposed approach extends the called column compaction in two ways. First, it is applied to the state-encoding bits in addition to the outputs, allowing a reduction in the number of logic functions required both by the state transition function and by the output function. Second, the technique exploits the dedicated multiplexers usually included in FPGAs to increase the number of columns that can be compacted. Unlike conventional state-encoding techniques, the proposed approach reduces the number of logic functions instead of their complexity. An Integer Linear Programming (ILP) formulation that maximizes the number of compacted columns has been proposed. In order to evaluate the effectiveness of the proposed approach, experimental results using standard benchmarks are presented. In most cases, the proposed approach reduces the number of used Look-Up Tables (LUTs) with respect to the conventional FSM implementation.

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Solving the State Assignment Problem Using Stochastic Search Aided with Simulated Annealing

Cited by 12 publications

References 8 publications

Modeling of Multi-Level Capacitated Lot-Size Scheduling Problem

Modeling of Multi-Level Capacitated Lot-Size Scheduling Problem

Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review

Mapping Outputs and States Encoding Bits to Outputs Using Multiplexers in Finite State Machine Implementations

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