Some aspects of reliability in amorphous chalcogenide memory switches

Abstract

It is shown that the statistical distribution of the lock-on time can predict the reliability of the set operation, which, in turn is influenced by the choice of reset parameters. Two modes of degradation of the threshold voltage are identified. One of these is impermanent and can be eliminated by the use of multiple reset pulses, while the other is permanent and is accelerated by the use of multiple reset pulses. An optimum of about 6 reset pulses is recommended. The impermanent mode is attributed to remnant crystalline debris while the permanent mode is attributed to electromigration.

Feedback write scheme for memristive switching devices

“…In PCM, the distribution of the switching delay time was found to be generally lognormal with a median that decreases with increasing SET current, i.e., the differential probability distribution function ∝ exp[−(ln t − t 0 ) 2 /τ ], where t 0 and τ are fitting parameters [11]. Distributions of other relevant physical parameters, such as the saturation nucleate size in PCM, were also found to be lognormal.…”

“…In fact, in RRAM devices, it is frequently observed that applying an unbounded voltage write pulse can produce large fluctuations in device resistances. The statistical distributions of resistance values, and other relevant parameters for device operation, e.g., switching delay time, exhibit a lognor-mal law, where the measured values are distributed over a much wider range than a more plausible normal distribution [11][12][13]. Such lognormal distributions of device parameters are a potential obstacle for the reliability and longevity of RRAM.…”