Some compact layouts of the butterfly

Dinitz, Yefim; Even, Shimon; Kupershtok, Roni; Zapolotsky, Maria

doi:10.1145/305619.305626

Cited by 9 publications

(10 citation statements)

References 9 publications

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“…To avoid confusion between the two representations of Figure 1 and Figure 2, the representation in Figure 1 will be called Rearrangeable representation of Benes and the representation in Figure 2 will be called VLSI representation of Benes. A similar representation for butterfly is studied by Dinitz et al [5,15].…”

Section: Proposed Vlsi Representation Of Benes Networkmentioning

confidence: 88%

“…The butterfly graphs have different representations including Omega network, the flip network, the baseline, and the reverse baseline networks. Each representation exhibits different characteristics [1,5,9,13]. In other words, the butterfly network is drawn in different ways to exhibit different properties.…”

Section: Mathematical Definition Of a Vlsi Layoutmentioning

confidence: 99%

“…Dinitz et al [5,15] have presented a layout whose encompassing rectangle is of area 1 2 2 2r + o(2 2r ), but this Downloaded by [New York University] at 06:19 06 August 2015 rectangle is 45 • slanted with respect to the grid axes. There are different models of VLSI layouts for butterfly-like architectures [14,15,16].…”

Section: A Simple Vlsi Layout Of Benes Networkmentioning

confidence: 99%

“…The paths of the layout are restricted to follow along grid tracks and are not allowed to overlap for any distance (although a vertical path segment may cross a horizontal path segment). If they change direction at this point, it is called a knockknee [5]. In addition, the paths may not cross nodes to which they are not adjacent [2].…”

Section: Introductionmentioning

confidence: 99%

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VLSI layout of Benes networks

Manuel

Qureshi

William³

et al. 2007

Journal of Discrete Mathematical Sciences and Cryptography

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The Benes network consists of back-to-back butterflies. There exist a number of topological representations that are used to describe butterfly -like architectures. We identify a new topological representation of Benes network. The significance of this representation is demonstrated by solving two problems, one related to VLSI layout and the other related to robotics. An important VLSI layout network problem is to produce the smallest possible grid area for realizing a given network. We propose an elegant VLSI layout of r-dimensional Benes networks using this representation. The area of this layout is O(2 2r ) whereas the lower bound for the area of the VLSI layout of Benes networks is O(2 2r ). This lower bound is estimated by applying Thompson result.

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Section: Proposed Vlsi Representation Of Benes Networkmentioning

confidence: 88%

Section: Mathematical Definition Of a Vlsi Layoutmentioning

confidence: 99%

Section: A Simple Vlsi Layout Of Benes Networkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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VLSI layout of Benes networks

Manuel

Qureshi

William³

et al. 2007

Journal of Discrete Mathematical Sciences and Cryptography

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“…Many results on layouts of various classes of graphs, such as planar graphs and trees, with efficient area and small aspect ratio of O(1) have been reported (e.g., [2], [6], [8], [13], [17], [25]). Layouts with efficient area and large aspect ratio was examined in [3], [4], [11].…”

Section: Layout Into Large Aspect Ratiomentioning

confidence: 99%

VLSI layout of trees into grids of minimum width

Matsubayashi¹

2003

Proceedings of the Fifteenth Annual ACM Symposium on Parallel Algorithms and Architectures - SPAA '03

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SUMMARYIn this paper we consider the VLSI layout (i.e., Manhattan layout) of graphs into grids with minimum width (i.e., the length of the shorter side of a grid) as well as with minimum area. The layouts into minimum area and minimum width are equivalent to those with the largest possible aspect ratio of a minimum area layout. Thus such a layout has a merit that, by "folding" the layout, a layout of all possible aspect ratio can be obtained with increase of area within a small constant factor. We show that an N -vertex tree with layout-width k (i.e., the minimum width of a grid into which the tree can be laid out is k) can be laid out into a grid of area O(N ) and width O(k). For binary tree layouts, we give a detailed trade-off between area and width: an N -vertex binary tree with layout-width k can be laid out into area O( k+α 1+α N ) and width k + α, where α is an arbitrary integer with 0 ≤ α ≤ √ N , and the area is existentially optimal for any k ≥ 1 and α ≥ 0. This implies that α = Ω(k) is essential for a layout of a graph into optimal area. The layouts proposed here can be constructed in polynomial time. We also show that the problem of laying out a given graph G into given area and width, or equivalently, into given length and width is NP-hard even if G is restricted to a binary tree.

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Laying Out the Interconnection Network of the Transpose Bijection

Even

Kupershtok

2002

Theory Comput. Systems

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Some compact layouts of the butterfly

Cited by 9 publications

References 9 publications

VLSI layout of Benes networks

VLSI layout of Benes networks

VLSI layout of trees into grids of minimum width

Laying Out the Interconnection Network of the Transpose Bijection

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