Sorena: New on Chip Network Topology Featuring Efficient Mapping and Simple Deadlock Free Routing Algorithm

Janidarmian, Majid; Bokharaie, Vahhab Samadi; Khademzadeh, Ahmad; Tavanpour, Misagh

doi:10.1109/cit.2010.395

Cited by 6 publications

(2 citation statements)

References 16 publications

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“…The aggressive integration of computation and communication elements has caused great challenges on the reliability of such systems. Many solutions have been proposed to sustain the reliability of a system, including remapping [Derin et al 2011], fault-tolerant routing algorithms [Ebrahimi et al 2012], and various topologies for implementing the communication infrastructure [Janidarmian et al 2010;Kariniemi and Nurmi 2005]. Improving the manufacturing process can help to increase the reliability, but it will become increasingly difficult in the future.…”

Section: Introductionmentioning

confidence: 99%

Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm

Ren

Liu

Yin

et al. 2015

ACM Trans. Reconfigurable Technol. Syst.

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With an increasing number of processing elements (PEs) integrated on a single chip, fault-tolerant techniques are critical to ensure the reliability of such complex systems. In current reconfigurable architectures, redundant PEs are utilized for fault tolerance. In the presence of faulty PEs, the physical topologies of various chips may be different, so the concept of virtual topology from network embedding problem has been used to alleviate the burden for the operating systems. With limited hardware resources, how to reconfigure a system into the most effective virtual topology such that the maximum repair rate can be reached presents a significant challenge. In this article, a new approach using a maximum flow (MF) algorithm is proposed for an efficient topology reconfiguration in reconfigurable architectures. In this approach, topology reconfiguration is converted into a network flow problem by constructing a directed graph; the solution is then found by using the MF algorithm. This approach optimizes the use of spare PEs with minimal impacts on area, throughput, and delay, and thus it significantly improves the repair rate of faulty PEs. In addition, it achieves a polynomial reconfiguration time. Experimental results show that compared to previous methods, the MF approach increases the probability to repair faulty PEs by up to 50% using the same redundant resources. Compared to a fault-free system, the throughput only decreases by less than 2.5% and latency increases by less than 4%. To consider various types of PEs in a practical application, a cost factor is introduced into the MF algorithm. An enhanced approach using a minimum-cost MF algorithm is further shown to be efficient in the fault-tolerant reconfiguration of heterogeneous reconfigurable architectures. . 2015. Efficient fault-tolerant topology reconfiguration using a maximum flow algorithm.

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Section: Introductionmentioning

confidence: 99%

Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm

Ren

Liu

Yin

et al. 2015

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

show abstract

“…With the increasing circuit density, the reliability of a manycore system has become one of the most important challenges. Many solutions have been proposed to sustain the reliability of a system, including remapping [2], fault tolerant routing algorithms [3] and various topologies for implementing the communication infrastructure [4]. Improving the manufacturing process can help to increase the reliability, but this approach will become increasingly difficult in the future.…”

Section: Introductionmentioning

confidence: 99%

A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures

Liu

Ren

Deng

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

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An approach using a minimum cost maximum flow algorithm is proposed for fault-tolerant topology reconfiguration in a Network-on-Chip system. Topology reconfiguration is converted into a network flow problem by constructing a directed graph with capacity constraints. A cost factor is considered to differentiate between processing elements. This approach maximizes the use of spare cores to repair faulty systems, with minimal impact on area, throughput and delay. It also provides a transparent virtual topology to alleviate the burden for operating systems.

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Overhead- and Performance-Aware Fault-Tolerant Architecture for Application-Specific Network-on-Chip

Koupaei

Khademzadeh

Janidarmian

2012

Lecture Notes in Electrical Engineering

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Sorena: New on Chip Network Topology Featuring Efficient Mapping and Simple Deadlock Free Routing Algorithm

Cited by 6 publications

References 16 publications

Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm

Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm

A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures

Overhead- and Performance-Aware Fault-Tolerant Architecture for Application-Specific Network-on-Chip

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