2020 IEEE Symposium on VLSI Technology 2020
DOI: 10.1109/vlsitechnology18217.2020.9265099
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SOT-MRAM Based Analog in-Memory Computing for DNN Inference

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Cited by 51 publications
(42 citation statements)
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“…PCM and ReRAM typically have ON-resistance of 10–100 kΩ, while FeFET can operate at ON-resistance of higher than 500 kΩ (Jerry et al, 2017 ). Emerging spintronic devices such as spin orbit torque (SOT)-MTJ can potentially work under MΩ ON-resistance, due to separated read/write paths (Doevenspeck et al, 2020 ). The ability of providing large ON-state resistance can potentially enable deployment of large crossbars with minimal impact on computing accuracy.…”
Section: Discussionmentioning
confidence: 99%
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“…PCM and ReRAM typically have ON-resistance of 10–100 kΩ, while FeFET can operate at ON-resistance of higher than 500 kΩ (Jerry et al, 2017 ). Emerging spintronic devices such as spin orbit torque (SOT)-MTJ can potentially work under MΩ ON-resistance, due to separated read/write paths (Doevenspeck et al, 2020 ). The ability of providing large ON-state resistance can potentially enable deployment of large crossbars with minimal impact on computing accuracy.…”
Section: Discussionmentioning
confidence: 99%
“…Magnetic devices are further challenged by limited readout resolutions due to the relatively small magneto-resistance effect in practical MTJs. Fortunately, emerging SOT-MTJ with separate read and write paths could lead to device optimized in new design space with possibly higher ON/OFF ratios (up to 6x larger TMR ratio) that could be better suited for neuromorphic computing (Ikeda et al, 2008 ; Doevenspeck et al, 2020 ). And novel materials such as half metal have been predicted to potentially boost the magnetoresistive signals in future (Bhatti et al, 2017 ).…”
Section: Discussionmentioning
confidence: 99%
“…It has been proposed that Boolean arithmetic computations can be done near or in the memory by modifying the peripheral circuits and hence help in the reduction of data movements [97]- [99]. Moreover, crossbar arrays of MRAM devices can execute analog MVM operations, where both in-memory processing of data and intrinsic hardware parallelism can be exploited [100]. Such a computing architecture provides an efficient hardware primitive for running DNNs, which heavily rely on MVM operations.…”
Section: Analog In-memory Computing With Mram Crossbar Arraysmentioning
confidence: 99%
“…SOT-MRAM, on the other hand, has no such restriction, since the write operation occurs through the underlying HM layer. This means, the tunneling barrier can be tuned for achieving higher R ON (> 1M) without affecting the writing operation [100]. One crucial point to consider while designing high R ON is the choice of V i used to encode the input vectors on the BL.…”
Section: B Design Considerations For Mram-based Crossbarsmentioning
confidence: 99%
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