SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

Abstract

Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB OPEN ACCESSJ. Low Power Electron. Appl. 2014, 4 189(silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed.Keywords: field programmable gate array (FPGA); static leakage power reduction; fine-grained body biasing; silicon on thin buried oxide (SOTB)

Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology

“…5, the FPGA tile area of this work is compared with that of the earlier work [13] and the recent work [14]. FPGA tiles of the recent work and this work are the horizontal line symmetry structure.…”

“…effective V t steps exploration [9], the trade-off evaluation between area and leakage current reduction on Vt programming granularity [10] and investigation of higher speed operation ability [11], the fully-functional power reconfigCopyright c 2016 The Institute of Electronics, Information and Communication Engineers urable FPGA chip on 90-nm bulk CMOS process is successfully realized [12]. Furthermore, 0.4-V power supply operation and effective static power reduction is demonstrated by implementing 32-bit binary counter to the FPGA on 65-nm SOTB (Silicon On Thin BOX) CMOS technology [13], [14].…”

“…In earlier works [12], [13], mask layout of whole chip is manually designed. Many design margins are needed to simplify the construction of mask layout.…”

Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device

“…We improved our synthesis tool chain [6] to support multiple modules, fixed values, and Verilog-HDL source files for facilitating the implementation of practical circuits. We employed yosys [7] and ABC [8] tools, and added prepossessing and post-processing to the module description file and the LUT mapping information.…”

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

“…This performance requirement means that 32-bit microprocessors that can work with a 20 MHz or higher clock are needed instead of the conventional tiny processors near the threshold level working with a hundreds of kilo Hertz operational clock. To fulfill these requirements, a novel FD-SOI technique called silicon on thin buried oxide (SOTB) has been developed [1] and implemented on low power microprocessors [2], accelerators [3], and FPGAs [4].…”