Source and Drain Junction Engineering for Enhanced Non-Volatile Memory Performance

Choi, Sung-Jin; Choi, Yang‐Kyu

doi:10.5772/18460

Cited by 9 publications

(5 citation statements)

References 15 publications

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“…A Schottky barrier cylindrical gate all around (CGAA) metaloxide-semiconductor field-effect transistor (MOSFET) with metal source/drain (S/D) instead of the usual highly doped S/D is an excellent candidate for low power, high speed and extremely scaled MOS devices in the nano regime [1]. It offers low S/D interface contact resistivity for metallic S/D compared with doped S/D [2]. It solves the major bottlenecks of device scaling such as a very shallow S/D junction, difficult doping techniques, and a thermal budget which makes it a futuristic alternative for next-generation MOS device [3,4].…”

Section: Introductionmentioning

confidence: 99%

Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

Kumar¹,

Haldar²,

Gupta³

et al. 2016

Semicond. Sci. Technol.

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The threshold voltage degradation due to the hot carrier induced localized charges (LC) is a major reliability concern for nanoscale Schottky barrier (SB) cylindrical gate all around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs). The degradation physics of gate material engineered (GME)-SB-GAA MOSFETs due to LC is still unexplored. An explicit threshold voltage degradation model for GME-SB-GAA-MOSFETs with the incorporation of localized charges (N it ) is developed. To accurately model the threshold voltage the minimum channel carrier density has been taken into account. The model renders how +/− LC affects the device subthreshold performance. One-dimensional (1D) Poisson's and 2D Laplace equations have been solved for two different regions (fresh and damaged) with two different gate metal work-functions. LCs are considered at the drain side with low gate metal work-function as N it is more vulnerable towards the drain. For the reduction of carrier mobility degradation, a lightly doped channel has been considered. The proposed model also includes the effect of barrier height lowering at the metal-semiconductor interface. The developed model results have been verified using numerical simulation data obtained by the ATLAS-3D device simulator and excellent agreement is observed between analytical and simulation results.

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Section: Introductionmentioning

confidence: 99%

Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

Kumar¹,

Haldar²,

Gupta³

et al. 2016

Semicond. Sci. Technol.

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“…To provide authenticity of our numerical simulation analysis for the proposed insulated shallow extension device, the results are calibrated with the published experimental data [9] . Calibrated electrical characteristics are shown in Fig.…”

Section: Device Calibrationmentioning

confidence: 99%

“…Schottky barrier (SB) CGAA MOSFET is one of the potential candidates for future ultra-scaled devices. SB-CGAA MOS-FET [8,9] with metal source/drain (MSD) provides several benefits over doped S/D i.e. low S/D interface contact resistivity (ρ c ) (for MSD, ρ c = 10 −9 Ω•cm compared to ρ c = 10 −7 Ω•cm for doped S/D) [10] , improved performance with undoped channel (lightly doped) and ease of low-temperature processing [11] .…”

Section: Introductionmentioning

confidence: 99%

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

et al. 2017

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In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The I ON /I OFF of ISE-CGAA-SB-MOS-FET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

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“…At nanoscale the junction depletion width (p-n) at SourceChannel (S-C) and Channel-Drain (C-D) junctions can not be neglected as it degrades the ON current due to increased S-C and C-D resistance [5][6][7][8] and is actively involved in MOSFET device performance. The Schottky Barrier (SB) Cylindrical Gate All Around (CGAA) MOSFET with lightly doped channel have attracted attention [9][10][11][12] to overcome the device fabrication challenges like abrupt source/drain formation as it offers low resistivity (ρ c ~10 -9 Ω.cm) of metallic source drain and no depletion in S/D regions [13]. It also reduces thermal budget of fabrication process [14].…”

Section: Introductionmentioning

confidence: 99%

Ambipolarity reduction in DMG asymmetric vacuum dielectric Schottky Barrier GAA MOSFET to improve hot carrier reliability

Kumar

Haldar

Gupta

et al. 2017

Superlattices and Microstructures

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Source and Drain Junction Engineering for Enhanced Non-Volatile Memory Performance

Cited by 9 publications

References 15 publications

Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

Ambipolarity reduction in DMG asymmetric vacuum dielectric Schottky Barrier GAA MOSFET to improve hot carrier reliability

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