Source-End Layout Influences on MOSFET ESD Protection Devices in a 0.35um 5V Process

Abstract

An nMOS transistor in input/output pad as the ESD protection element is usually in the form of multi-finger layout. This paper will show simple but effective ways to improve an nMOSFET’s ESD robustness or LU immunity for use in I/O pads, i.e., the source-end layout influences on the protection components in ESD/LU capabilities of the input/output pads will be investigated. In other words, they are used to increase the effective ESD or LU capability of the ESD protection elements. Here, the different source-end layout types will be carried out the important snapback parameters. We focus on exploring the secondary breakdown current (It2) and holding voltage (Vh) for the ESD discharge capability and the latch-up immunity, hopefully, it does effectively enhance ESD/LU robustness.