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A multi-finger nMOST is widely used as an electrostatic discharge (ESD) protection device especially in the input/output pads. However, the contact-spiking leakage phenomenon in an MOST are seriously impacted the ESD capability. Therefore, one drain-side engineering is investigated in this paper, i.e., by adding a negative-type well (nWell) structure in the drain-side of device, hoping to avoid contact-spiking issues to enhance ESD reliability. The nWell width variations will be explored the influence on snapback parameters of ESD devices in a 0.35μm 3.3V low voltage (LV) process. However, after a systematic analysis, it is found that adding an nWell structure in the drain-side will lower ESD capability (It2 value) about 24% for this process. And, as compared with the original reference DUT, adding any nWell in the drain-side will make the Vh value slightly decreasing about 1%.

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An nMOS transistor in input/output pad as the ESD protection element is usually in the form of multi-finger layout. This paper will show simple but effective ways to improve an nMOSFET’s ESD robustness or LU immunity for use in I/O pads, i.e., the source-end layout influences on the protection components in ESD/LU capabilities of the input/output pads will be investigated. In other words, they are used to increase the effective ESD or LU capability of the ESD protection elements. Here, the different source-end layout types will be carried out the important snapback parameters. We focus on exploring the secondary breakdown current (It2) and holding voltage (Vh) for the ESD discharge capability and the latch-up immunity, hopefully, it does effectively enhance ESD/LU robustness.

No abstract