Intelligent Technologies and Engineering Systems
 2013
DOI: 10.1007/978-1-4614-6747-2_60
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Source-End Layouts on ESD/LU Reliabilities in an HV 0.25 um 60 V nLDMOS

Shen Li Chen
1
,
Min Hua Lee
2
,
Tzung Shian Wu
3
et al.
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