1994
DOI: 10.1109/23.340574
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Space radiation evaluation of 16 Mbit DRAMs for mass memory applications

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Cited by 36 publications
(6 citation statements)
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“…We have not focused on any one specific DRAM or SRAM, but rather on a representative sampling of RAMs to show that the correlation applies to both SRAMs and DRAMs, and applies fairly well regardless of which commercially available RAM is used (however this is not true for those RAMs specifically designed to have a low SEU sensitivity, e.g. the IBM LUNA-C andEi DRAMs [26]). …”
Section: Discussionmentioning
confidence: 97%
“…We have not focused on any one specific DRAM or SRAM, but rather on a representative sampling of RAMs to show that the correlation applies to both SRAMs and DRAMs, and applies fairly well regardless of which commercially available RAM is used (however this is not true for those RAMs specifically designed to have a low SEU sensitivity, e.g. the IBM LUNA-C andEi DRAMs [26]). …”
Section: Discussionmentioning
confidence: 97%
“…Recently, radiation-hardened field programmable gate arrays (FPGAs) having up to 1 Mrad total ionizing dose (TID) tolerance are available [3]- [7]. However, since the radiation levels of some areas close to containment vessels in the Fukushima Daiichi Nuclear Power Plant are presumed to have radiation levels higher than 100 Sv/h, an embedded system constructed for space-grade devices would not have sufficient radiation tolerance for use in such areas.…”
Section: Introductionmentioning
confidence: 99%
“…[6] Single-bit upsets were observed and attributed to direct strikes to memory cells . No doubles, triples, etc were observed.…”
Section: Discussionmentioning
confidence: 98%
“…MPTB also provides the addresses of all the memory cells that upset, and, together with the bitmap, it is possible to determine their spatial relationship. Four recognized mechanisms responsible for MBU's are; i) charge diffusion away from an ion track and collection by adjacent SEU-sensitive nodes [3,4], ii) charge collected from an ion track passing through the circuit just below the surface and intersecting a number of memory cells in a straight line [ 5 ] , iii) ion strikes to control circuitry [6], and iv) proton-induced recoils and reaction products. All four of these mechanisms have been invoked to explain the origins of MBU's observed in the DRAM's and SRAM's on board MPTB.…”
Section: Introductionmentioning
confidence: 99%