SpaceCube v2.0 space flight hybrid reconfigurable data processing system

Abstract

This paper details the design architecture, design methodology, and the advantages of the SpaceCube v2.0 high performance data processing system for space applications.The purpose in building the SpaceCube v2.0 system is to create a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. The SpaceCube v2.0 system leverages seven years of board design, avionics systems design, and space flight application experiences.This paper shows how SpaceCube v2.0 solves the increasing computing demands of space data processing applications that cannot be attained with a standalone processor approach.The main objective during the design stage is to find a good system balance between power, size, reliability, cost, and data processing capability. These design variables directly impact each other, and it is important to understand how to achieve a suitable balance. This paper will detail how these critical design factors were managed including the construction of anEngineering Model for an experiment on the International Space Station to test out design concepts. We will describe the designs for the processor card, power card, backplane, and a mission unique interface card. The mechanical design for the box will also be detailed since it is critical in meeting the stringent thermal and structural requirements imposed by the processing system. In addition, the mechanical design uses advanced thermal conduction techniques to solve the internal thermal challenges.The SpaceCube v2.0 processing system is based on an extended version of the 3U cPCI standard form factor where each card is 190mm x IOOmm in size. The typical power draw of the processor card is 8 to lOW and scales with application complexity. The SpaceCube v2.0 data processing card features two Xilinx Virtex-5 QV Field Programmable Gate Arrays (FPGA), eight memory modules, a monitor FPGA with analog monitoring, Ethernet, configurable interconnect to the Xilinx FPGAs including gigabit transceivers, and the necessary voltage regulation. The processor board uses a back-to-back design methodology for common parts that maximizes the board real estate available. This paper will show how to meet the IPC 6012B Class 3/A standard with a 22-layer board that has two column grid array devices with 1.0mm pitch. All layout trades such as stack-up options, via selection, and FPGA signal breakout will be discussed with feature size results. The overall board design process will be discussed including parts selection, circuit design, proper signal termination, layout placement and route planning, signal integrity design and verification, and power integrity results. The radiation mitigation techniques will also be detailed including configuration scrubbing options, Xilinx circuit mitigation and FPGA functional monitoring, and memory protection. U.S. Government work not protected by U.S. copyrightFinally, this paper will describe how this system is bein...

MISR-GOES 3D Winds: Implications for Future LEO-GEO and LEO-LEO Winds

“…An example of disparities calculated in a test of an FPGA implementation suitable for a CubeSat mission. The implementation of Hirschmuller's algorithm[67] in the SpaceCube 2.0 processor[68] will be tested onboard the International Space Station in late 2019.…”

Adapting the SpaceCube v2.0 data processing system for mission-unique application requirements

“…There is a growing need for higher performance processing systems for space as instruments/spacecrafts levy tougher electrical interfacing and data bandwidth requirements on the computing node of the system. In addition, on-board processing of the data products, in some cases in real-time, is now a common requirement [1].…”

“…Typical space processing systems generally consist of a single radiation hardened processor which deliver less than 300 DMIPS along with an anti-fuse FPGA element [1]. These processors are not good candidates for applications that require fast computations of complex algorithms on a high bandwidth or large volume data source.…”

“…The backplane is designed as point-to-point so each I/O card does not require a PCI controller. The entire system including details on design methodology, architecture, card descriptions, mechanical packaging, and analyses is fully described in [1].…”

“…The v2.0 processor card infrastructure supports on-orbit reconfiguration that was proven on the v1.0 system on the ISS [2,10]. Referencing Figure 6 in [1], the Aeroflex FPGA configures the Xilinx FPGAs with initial configuration files that are stored in PROM. Reconfiguration is achieved by allowing the Xilinx FPGAs to reconfigure each other with design files that are stored in Flash.…”