SPAID: software prefetching in pointer- and call-intensive environments

Lipasti, Mikko H.; Schmidt, William J.; Kunkel, S.; Roediger, Robert R.

doi:10.1109/micro.1995.476830

Cited by 68 publications

(46 citation statements)

References 32 publications

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“…Most prefetching techniques, for example, are speculative in nature and rely on some heuristic for generating addresses of future memory references (e.g. [21,22,23,24,25]). Of course, since prefetching has no architected side effects, no mechanism is needed for verifying the accuracy of the prediction or for recovering from mispredictions.…”

Section: Data Speculationmentioning

confidence: 99%

Exceeding the dataflow limit via value prediction

Lipasti

Shen

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29

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186

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Meanwhile, numerous mechanisms have been proposed and implemented to eliminate false data dependences and tolerate the latencies induced by true data dependences by allowing instructions to execute out of program order (see [8] for an overview).Surprisingly, in light of the extensive energies focused on eliminating control-flow restrictions on parallel instruction issue, less attention has been paid to eliminating data-flow restrictions on parallel issue. Recent work has focused primarily on reducing the latency of specific types of instructions (usually loads from memory) by rearranging pipeline stages [9,10], initiating memory accesses earlier [11], or speculating that dependences to earlier stores do not exist [12,13,14,15].The most relevant prior work in the area of eliminating data-flow dependences consists of the Tree Machine [16,17], which uses a value cache to store and look up the results of recurring arithmetic expressions to eliminate redundant computation (the value cache, in effect, performs common subexpression elimination [1] in hardware). Richardson follows up on this concept in [18] by introducing the concepts of trivial computation, which is defined as the trivialization of potentially complex operations by the occurrence of simple operands; and redundant computation, where an operation repeatedly performs the same computation because it sees the same operands. He proposes a hardware mechanism (the result cache) which reduces the latency of such trivial or redundant complex arithmetic operations by storing and looking up their results in the result cache.

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Section: Data Speculationmentioning

confidence: 99%

Exceeding the dataflow limit via value prediction

Lipasti

Shen

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29

Self Cite

265

186

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“…al. [10] which heuristically dereferenced pointers passed into procedures. Luk and Mowry [11] discussed several software techniques, including compiler-based greedy prefetching, programmer-controlled history pointer prefetching (essentially software full jumping), and data linearization.…”

Section: Related Workmentioning

confidence: 99%

Effective jump-pointer prefetching for linked data structures

Roth

Sohi

Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)

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“…[26]. Beyond loops, prefetching for procedure parameters [21] and recursive data structures [23] have also been proposed. Karlsson, Dahlgren, and Stenstrom [17] proposed the use of prefetch arrays while VanderWiel and Lilja proposed a data prefetch controller (DPC) [29].…”

Section: Related Workmentioning

confidence: 99%

Targeted Data Prefetching

Wong

2005

Advances in Computer Systems Architecture

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Abstract. Given the increasing gap between processors and memory, prefetching data into cache becomes an important strategy for preventing the processor from being starved of data. The success of any data prefetching scheme depends on three factors: timeliness, accuracy and overhead. In most hardware prefetching mechanism, the focus has been on accuracy -ensuring that the predicted address do turn out to be demanded in a later part of the code. In this paper, we introduce a simple hardware prefetching mechanism that targets delinquent loads, i.e. loads that account for a large proportion of the load misses in an application. Our results show that our prefetch strategy can reduce up to 45% of stall cycles of benchmarks running on a simulated out-of-order superscalar processor with an overhead of 0.0005 prefetch per CPU cycle.

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SPAID: software prefetching in pointer- and call-intensive environments

Cited by 68 publications

References 32 publications

Exceeding the dataflow limit via value prediction

Exceeding the dataflow limit via value prediction

Effective jump-pointer prefetching for linked data structures

Targeted Data Prefetching

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