Sparse Dense Neural Network Architecture for Turbo Decoding

Vankayala, Satya Kumar; Kumar, Swaraj; Thirumulanathan, D; Yoon, Seungil; Kommineni, Issaac; S, Lakshmi Narayana V

doi:10.1109/ants52808.2021.9936903

Cited by 1 publication

(1 citation statement)

References 9 publications

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“…Turbo iterative decoding improves channel coding performance and error correction capability through the use of iteration and feedback mechanisms. It is particularly effective in high signal-tonoise ratios and challenging transmission environments, where it can significantly enhance system performance [9]. As the turbo encoder employs two identical convolutional encoders and the interleaver and deinterleaver have been merged, the turbo iterative decoder can be simplified as shown in Figure 5.…”

Section: Turbo Decodermentioning

confidence: 99%

Implementation of turbo decoding for VDES signal data segments

Zhang,

Wang

2024

J. Phys.: Conf. Ser.

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The International Telecommunication Union (ITU) mandates the use of turbo coding for VDES signal data segments. Previous studies primarily focused on turbo decoding for a specific link in VDES, often neglecting its applicability to all links. This paper proposes an FPGA-based implementation method for turbo code decoding, aiming to achieve fast and accurate turbo decoding of VDES signal data segments, while also ensuring compatibility with different links. The resulting turbo decoder can adapt to the different code rates and data segment lengths specified in the VDES. A comparison of the decoding speeds between DSP and FPGA confirms that the parallel computing capability of FPGA can significantly improve the decoding speed. Finally, the main onboard resources required for FPGA implementation of turbo decoding were provided.

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Section: Turbo Decodermentioning

confidence: 99%