SparTen

Gondimalla, Ashish; Chesnut, Noah; Thottethodi, Mithuna; Vijaykumar, T. N.

doi:10.1145/3352460.3358291

Cited by 191 publications

(24 citation statements)

References 22 publications

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“…through pruning can help mitigate the computation complexity [26][27][28][29][30][31]. More efficient ways of using the computation hardware infrastructure, including static or dynamic exploitation of value sparsity to avoid unnecessary computation, are also being developed [32][33][34][35][36][37][38]. These are all valuable efforts to mitigate the complexity explosion and to help sustain the continuation of the current productive trends.…”

Section: Figure Taken Frommentioning

confidence: 99%

Cortical Columns Computing Systems: Microarchitecture Model, Functional Building Blocks, and Design Tools

Shen¹,

Nair²

2023

Neuromorphic Computing

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Reverse-engineering the human brain has been a grand challenge for researchers in machine learning, experimental neuroscience, and computer architecture. Current deep neural networks (DNNs), motivated by the same challenge, have achieved remarkable results in Machine Learning applications. However, despite their original inspiration from the brain, DNNs have largely moved away from biological plausibility, resorting to intensive statistical processing on huge amounts of data. This has led to exponentially increasing demand on hardware compute resources that is quickly becoming economically and technologically unsustainable. Recent neuroscience research has led to a new theory on human intelligence, that suggests Cortical Columns (CCs) as the fundamental processing units in the neocortex that encapsulate intelligence. Each CC has the potential to learn models of complete objects through continuous predict-sense-update loops. This leads to the overarching question: Can we build Cortical Columns Computing Systems (C3S) that possess brain-like capabilities as well as brain-like efficiency? This chapter presents ongoing research in the Neuromorphic Computer Architecture Lab (NCAL) at Carnegie Mellon University (CMU) focusing on addressing this question. Our initial findings indicate that designing truly intelligent and extremely energy-efficient C3S-based sensory processing units, using off-the-shelf digital CMOS technology and tools, is quite feasible and very promising, and certainly warrants further research exploration.

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Section: Figure Taken Frommentioning

confidence: 99%

Cortical Columns Computing Systems: Microarchitecture Model, Functional Building Blocks, and Design Tools

Shen¹,

Nair²

2023

Neuromorphic Computing

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“…The values are delivered to an array of multipliers, and the resulting scattered products are summed using a dedicated interconnection mesh. Sparten [70] is based on SCNN architecture, but it improves the distribution of the operations to the multipliers to reduce the overhead. EIE [71] compresses the weights with the CSC scheme and has zero-skipping ability for null activations.…”

Section: Accelerators With Sparsity Exploitationmentioning

confidence: 99%

An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks

et al. 2020

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Deep Neural Networks (DNNs) are nowadays a common practice in most of the Artificial Intelligence (AI) applications. Their ability to go beyond human precision has made these networks a milestone in the history of AI. However, while on the one hand they present cutting edge performance, on the other hand they require enormous computing power. For this reason, numerous optimization techniques at the hardware and software level, and specialized architectures, have been developed to process these models with high performance and power/energy efficiency without affecting their accuracy. In the past, multiple surveys have been reported to provide an overview of different architectures and optimization techniques for efficient execution of Deep Learning (DL) algorithms. This work aims at providing an up-to-date survey, especially covering the prominent works from the last 3 years of the hardware architectures research for DNNs. In this paper, the reader will first understand what a hardware accelerator is, and what are its main components, followed by the latest techniques in the field of dataflow, reconfigurability, variable bit-width, and sparsity.

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“…While we explore further workloads in Section 3.3, our main motivation is accelerating general sparse LA on a set of established tensor formats. Unlike approaches focused on low sparsities [10], [11], [17], SSSRs target flexibility and scalability to achieve notable speedups across a wider sparsity range (see Section 4.1). SSSRs support iterating along the major axis of any tensor format where said axis is given by two arrays: a value array storing nonzero values and an index array storing their positions.…”

Section: Accelerable Formats and Operationsmentioning

confidence: 99%

“…Most general-purpose instruction set architecture (ISA) extensions consider only one-sided sparsity [8], [9], and those targeting sparse-sparse workloads incur large area impacts and cannot efficiently handle the former [6]. Sparse ML solutions often rely on custom, domain-specific formats and low or structured sparsity [10], [11], while more general sparse LA accelerators [12], [13] incur significant silicon area impacts compared to their host systems and other solutions.…”

Section: Introductionmentioning

confidence: 99%

Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra

Scheffler

Zaruba

Schuiki

et al. 2021

2021 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Sparse linear algebra is crucial in many application domains, but challenging to handle efficiently in both software and hardware, with one-and two-sided operand sparsity handled with distinct approaches. In this work, we enhance an existing memorystreaming RISC-V ISA extension to accelerate both one-and two-sided operand sparsity on widespread sparse tensor formats like compressed sparse row (CSR) and compressed sparse fiber (CSF) by accelerating the underlying operations of streaming indirection, intersection, and union. Our extensions enable single-core speedups over an optimized RISC-V baseline of up to 7.0x, 7.7x, and 9.8x on sparse-dense multiply, sparse-sparse multiply, and sparse-sparse addition, respectively, and peak FPU utilizations of up to 80% on sparse-dense problems. On an eight-core cluster, sparse-dense and sparse-sparse matrix-vector multiply using real-world matrices are up to 5.0x and 5.9x faster and up to 2.9x and 3.0x more energy efficient. We explore further applications for our extensions, such as stencil codes and graph pattern matching. Compared to recent CPU, GPU, and accelerator approaches, our extensions enable higher flexibility on data representation, degree of sparsity, and dataflow at a minimal hardware footprint, adding only 1.8% in area to a compute cluster. A cluster with our extensions running CSR matrix-vector multiplication achieves 69x and 2.8x higher peak floating-point utilizations than recent CPU and GPU software, respectively.

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SparTen

Cited by 191 publications

References 22 publications

Cortical Columns Computing Systems: Microarchitecture Model, Functional Building Blocks, and Design Tools

Cortical Columns Computing Systems: Microarchitecture Model, Functional Building Blocks, and Design Tools

An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks

Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra

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