SPC08-6: A Histogram-based Symbol Timing Synchronization Algorithm for OFDM Systems

Lin, Hsin-De; Sang, Tzu-Hsien; Hsu, Sheng-Yi

doi:10.1109/glocom.2006.579

Cited by 1 publication

(1 citation statement)

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“…Assuming the CP is already present, this method does not incur additional overhead and gathers information continuously. However, it is susceptible to phase-error detection unreliability when severe ISI and low SNR are present [14], [21], [24]. Although reliability can be improved by time averaging, this lowers the jitter tracking bandwidth [20].…”

Section: ) Use Of Cyclic Prefixmentioning

confidence: 99%

Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications

Cosson-Martin

Shakiba

Sheikholeslami

2021

IEEE Open J. Circuits Syst.

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This paper proposes a discrete multi-tone timing-recovery system with adaptive equalization for ultra-high-speed wireline applications. It combines frequency-domain clock recovery with decisiondirected equalization to improve receiver performance while eliminating the need for pilot carriers, thereby increasing spectral efficiency. Compared to a conventional pilot-carrier-based technique employing four pilot carriers and a 32-point FFT, this approach improves phase-error sensitivity by 3.6 times, tracking bandwidth by 1.7 times, increases the jitter tolerance slope by 20dB per decade at low frequency, and removes residual equalization error, resulting in an overall data-rate increase of 27%. The concept is validated at the system-level and gate-level through synthesis in an FPGA. A convergence analysis of both the adaptive equalizer and clock synchronization shows the system's ability to mitigate error propagation and remain synchronized in the presence of impairments. Finally, we highlight the system's ability to trade-off clock convergence versus phase error sensitivity. Either parameter can be adjusted by 15 times, optimizing the receiver over a broad range of signal conditions.INDEX TERMS Adaptive equalization, clock and data recovery (CDR), decision-directed equalization, discrete multi-tone (DMT), orthogonal frequency division multiplexing (OFDM), SERDES, single-tap equalization, timing recovery, wireline. JEREMY COSSON-MARTIN (Graduate Student Member, IEEE) received the B.A.Sc. degree in electrical engineering from Queen's University, Kingston, ON, Canada, in the spring of 2018. In the fall of 2018, he began an M.A.Sc. program at the University of Toronto, ON, Canada, under the supervision of Prof. A. Sheikholeslami. In 2019, he transferred into a Ph.D. program.In the summer of 2018, he joined Huawei Canada, Toronto, ON, Canada, as an intern, where he was involved in creating in-lab measurement scripts for a prototype 56-Gb/s SerDes integrated chip. He also received experience in 7-nm FinFET layout. Currently, he is researching multi-tone schemes for ultra-high-speed wireline applications.

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Section: ) Use Of Cyclic Prefixmentioning

confidence: 99%