Special purpose FPGA for high-speed digital telecommunication systems

Tsutsui, Akihiro; Miyazaki, Toshiaki; Yamada, K.; Ohta, Nobuhiro

doi:10.1109/iccd.1995.528912

Cited by 13 publications

(6 citation statements)

References 5 publications

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“…The MAX-9000 array card also has an architecture such as that shown in Figure 7. Furthermore, we nm planning to develop a new type of FPGA card which contains our original PPGA device [4] using a new compact package version of it.…”

Section: Fpga Card and Mpu Cardmentioning

confidence: 99%

“…In such a situation, we considered that a Field Programmable Gate Amty (FPGA) is the key device of future telecommunication systems and have developed an original FPGA especially designed for high-speed telecommunication data p rousing [4][5J. Using this device, we also u~nsttucti a reconfigurable signal-transport system dedicated to realtime emulation of transport p romshg circuits [6].…”

Section: Introductionmentioning

confidence: 99%

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Yards

Tsutsui

Miyazaki

1997

Proceedings of the 1997 ACM Fifth International Symposium on Field-Programmable Gate Arrays - FPGA '97

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This paper presents a novel system architecture applicable to highperformance and flexible transport data processing which includes complex protocol operation and a network control algorithm. We developed a new tightly coupled Field Programmable Gate Army (FPGA) and hIicroProc&ng Unit (MPU) system named Yet Another Re-Definable System (YARDS). It comprises three programmable devices which equate to high flexibility. These devices are the RISC-type MPU with memories, programmable inter-connection devices, and FPGAs. Using these, this system supports various styles Of coupling Ween the FPGAs and the MPU which are suitable for constructing transport data processing. In this paper, two applications of the system in the telecommunications field are given. One is an Operation, Administration, and Management (OAM) cell operations on an Asynchronous Transfer Mode (ATM) network The other is a dynamic recontiguration protocol enables the update or change of the functions of the transport data processing system on-line. This is the first approach applying the FPGAMPU hybrid system to the telecommunications field.

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Section: Fpga Card and Mpu Cardmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Yards

Tsutsui

Miyazaki

1997

Proceedings of the 1997 ACM Fifth International Symposium on Field-Programmable Gate Arrays - FPGA '97

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“…The proposed algorithm has been implemented on SUN Sparc Station 2 (28.5 MIPS) in C language and experimented on PROTEUS, a transport-processing FPGA chip [4], [8], [9]. Table I summarizes puts, LUTs, and latches (#inputs, #outputs, #LUTs, and #FFs, respectively) of transport-processing circuits to be experimented.…”

Section: Resultsmentioning

confidence: 99%

“…1 based on an FPGA chip proposed in [4], [8], [9]. The model has a two-dimensional array of basic cells.…”

Section: A Fpga Modelmentioning

confidence: 99%

“…As application-specific field-programmable gate arrays (FPGAs), transport-processing FPGAs have been proposed [4], [8], [9].1 In contrast with conventional FPGAs as in [lo], transport-processing FPGAs have finer granularity of logic functions so that they implement more flexible circuits on them. Since transport data processing has strong direction of signal flows, input terminals ~ FPGAs called PROTEIJS have been developed for transport processing [4] ,[SI, [Y].…”

Section: Introductionmentioning

confidence: 99%

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A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs

Togawa

Sato²,

Ohtsuki³

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

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In layout design of transport-processing FPGAs, it is required t h a t not only routing congestion is kept small but also circuits implemented on t h e m operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FP-GAS whose objective is to minimize routing congestion and proposes a new algorithm in which t h e length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on hierarchical bipartitioning of layout regions and LUT (Lookup Table) sets t o be placed. Each bipartitioning procedure consists of three phases: ( 0 ) estimation of p a t h lengths, (1) bipartitioning of a set of terminals, and (2) bipartitioning of a set of LUTs. After searching t h e paths with tighter path length constraints by estimating path lengths in ( O ) , (1) and (2) are executed so t h a t their path lengths are reduced with higher priority and thus p a t h length constraints are not violated. T h e algorithm has been implemented and applied t o transport-processing circuits compared with conventional approaches. T h e results demonstrate t h a t t h e algorithm resolves path length constraints for 11 out of 13 circuits, though it increases routing congestion by a n average of 20%. After detailed routing, it achieves 100% routing for all t h e circuits and decreases a circuit delay by a n average of 23%.

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