Speed binning with path delay test in 150-nm technology

Cory, Bruce; Kapur, R.; Underwood, B.

doi:10.1109/mdt.2003.1232255

Cited by 97 publications

(32 citation statements)

References 11 publications

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“…Traditional parametric yield analysis of high-performance integrated circuits is done using the frequency (or speed) binning method [12]. For a given lot, each chip is characterized according to its operating frequency and figuratively placed in a particular bin according to this value.…”

Section: Yield Analysismentioning

confidence: 99%

Parametric yield estimation considering leakage variability

Rao

Devgan²,

Blaauw

et al. 2004

Proceedings of the 41st Annual Design Automation Conference

114

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Leakage current has become a stringent constraint in modern processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inverse correlation with circuit delay, effective parametric yield prediction must consider the dependence of leakage current on frequency. In this paper, we present a new chip-level statistical method to estimate the total leakage current in the presence of within-die and die-to-die variability. We develop a closed-form expression for total chip leakage that models the dependence of the leakage current distribution on a number of process parameters. The model is based on the concept of scaling factors to capture the effects of within-die variability. Using this model, we then present an integrated approach to accurately estimate the yield loss when both frequency and power limits are imposed on a design. Our method demonstrates the importance of considering both these limiters in calculating the yield of a lot.

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Section: Yield Analysismentioning

confidence: 99%

Parametric yield estimation considering leakage variability

Rao

Devgan²,

Blaauw

et al. 2004

Proceedings of the 41st Annual Design Automation Conference

114

View full text Add to dashboard Cite

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“…REACTIVE CLOCKS WITH VARIABILITY-TRACKING JITTER Various techniques have been proposed to mitigate the impact of variability. Parametric binning [9] performs at-speed testing to eliminate margins associated with global static variability, while Adaptive Clocks (AClk) attack dynamic variability by modifying the clock frequency when sensing changes in the operating conditions [7], [10], [11]. Unfortunately, the aforementioned techniques cannot get rid of some guardband margins because they cannot handle fast variability efficiently-more details are provided in Section VIII.…”

Section: Variability Margins and Static Timing Analysismentioning

confidence: 99%

Reactive clocks with variability-tracking jitter

Cortadella

Lavagno

López

et al. 2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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Abstract-The growing variability in nanoelectronic devices, due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging), requires increasing design guardbands, forcing circuits to work with conservative clock frequencies. Various schemes for clock generation based on ring oscillators and adaptive clocks have been proposed with the goal to mitigate the power and performance losses attributable to variability. However, there has been no systematic analysis to quantify the benefits of such schemes and no signoff method has been proposed for timing correctness. This paper presents and analyzes a Reactive Clocking scheme with Variability-Tracking Jitter (RClk) that uses variability as an opportunity to reduce power by continuously adjusting the clock frequency to the varying environmental conditions, and thus, reduces guardband margins significantly. Power can be reduced between 20% and 40% at iso-performance and performance can be boosted by similar amounts at iso-power. Additionally, energy savings can be translated to substantial advantages in terms of reliability and thermal management. More importantly, the technology can be adopted with minimal modifications to conventional EDA flows.

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“…The testing may be structural or functional in nature [5], [8], [9]. The total test time depends on the search procedure, the number of speed bins, and the frequency distribution of the processor.…”

Section: Introductionmentioning

confidence: 99%

Variation-aware speed binning of multi-core processors

Sartori

Pant

Kumar

et al. 2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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Abstract-Number of cores per multi-core processor die, as well as variation between the maximum operating frequency of individual cores, is rapidly increasing. This makes performance binning of multi-core processors a non-trivial task. In this paper, we study, for the first time, multi-core binning metrics and strategies to evaluate them efficiently. We discuss two multi-core binning metrics with high correlation to processor throughput for different types of workloads and different process variation scenarios. More importantly, we demonstrate the importance of leveraging variation model data in the binning process to significantly reduce the binning overhead with a negligible loss in binning quality. For example, we demonstrate that the performance binning overhead of a 64-core processor can be decreased by 51% and 36% using the proposed variationaware core clustering and curve fitting strategies respectively. Experiments were performed using a manufacturing variation model based on real 65nm silicon data.

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Speed binning with path delay test in 150-nm technology

Cited by 97 publications

References 11 publications

Parametric yield estimation considering leakage variability

Parametric yield estimation considering leakage variability

Reactive clocks with variability-tracking jitter

Variation-aware speed binning of multi-core processors

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