Variation-aware speed binning of multi-core processors

Sartori, John; Pant, Aashish; Kumar, Rakesh; Gupta, Puneet

doi:10.1109/isqed.2010.5450442

Cited by 26 publications

(28 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore, with the emergence of multi-core technology, intra-die variation has also become an issue. To minimize the overheads of guardbanding, recent efforts have shown that exploiting the inherent variation in devices [6], [7] yields significant improvements in overall system performance.…”

Section: Introductionmentioning

confidence: 99%

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings

Gottscho

Bathen

Dutt

et al. 2015

IEEE Trans. Comput.

Self Cite

View full text Add to dashboard Cite

Abstract-Hardware variability is predicted to increase dramatically over the coming years as a consequence of continued technology scaling. In this paper, we apply the Underdesigned and Opportunistic Computing (UnO) paradigm by exposing system-level power variability to software to improve energy efficiency. We present ViPZonE, a memory management solution in conjunction with application annotations that opportunistically performs memory allocations to reduce DRAM energy. ViPZonE's components consist of a physical address space with DIMM-aware zones, a modified page allocation routine, and a new virtual memory system call for dynamic allocations from userspace. We implemented ViPZonE in the Linux kernel with GLIBC API support, running on a real x86-64 testbed with significant access power variation in its DDR3 DIMMs. We demonstrate that on our testbed, ViPZonE can save up to 27.80 percent memory energy, with no more than 4.80 percent performance degradation across a set of PARSEC benchmarks tested with respect to the baseline Linux software. Furthermore, through a hypothetical "what-if" extension, we predict that in future non-volatile memory systems which consume almost no idle power, ViPZonE could yield even greater benefits, demonstrating the ability to exploit memory hardware variability through opportunistic software.

show abstract

Section: Introductionmentioning

confidence: 99%

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings

Gottscho

Bathen

Dutt

et al. 2015

IEEE Trans. Comput.

Self Cite

View full text Add to dashboard Cite

show abstract

“…There are a few strategies that are commonly adopted to combat the process variation problems. For example, performance (or speed) binning approach, which intends to pack processors into different classes based on their maximum operating frequencies, is a common method for profit maximization in the presence of frequency variation [37,140]. Performance binning is good for single core chips, however, it cannot capture the characteristic of a multi-core system.…”

Section: Uncertainty In Computing Infrastructuresmentioning

confidence: 99%

“…For example, performance/speed binning technique has been widely used to cluster chips with similar performance (e.g., frequency, leakage power) [141,122]. However, this approach didn't consider within-die variation.…”

Section: Related Work On Process Variationmentioning

confidence: 99%

“…[141]) to cluster chips with similar performance. As a result, even in the presence of large manufacturing variations, processors of the same grade have less performance variations.…”

Section: Related Workmentioning

confidence: 99%

“…Besides extensive work on layout and device level, there are increasing research efforts to address the process variation problem from architecture and system level. For example, performance binning technique is proposed to cluster chips with similar performance [141,122]. However, this approach cannot deal with process variation of different cores within the same chip.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

On the Design of Real-Time Systems on Multi-Core Platforms under Uncertainty

Wang¹

View full text Add to dashboard Cite

To ensure timing constraints, traditional real-time system designs usually adopt a worst-case based deterministic approach. However, such an approach is becoming out of sync with the continuous evolution of IC technology and increased complexity of real-time applications. As IC technology continues to evolve into the deep submicron domain, process variation causes processor performance to vary from die to die, chip to chip, and even core to core. The extensive resource sharing on multicore platforms also significantly increases the uncertainty when executing real-time tasks. The traditional approach can only lead to extremely pessimistic, and thus, unpractical design of real-time systems.Our research seeks to address the uncertainty problem when designing real-time systems on multi-core platforms. We first attacked the uncertainty problem caused by process variation. We proposed a virtualization framework and developed techniques to optimize the system's performance under process variation. We further studied the problem on peak temperature minimization for real-time applications on multi-core platforms. Three heuristics were developed to reduce the peak temperature for real-time systems. Next, we sought to address the uncertainty problem vi in real-time task execution times by developing statistical real-time scheduling techniques. We studied the problem of fixed-priority real-time scheduling of implicit periodic tasks with probabilistic execution times on multi-core platforms. We further extended our research for tasks with explicit deadlines. We introduced the concept of harmonic to a more general task set, i.e. tasks with explicit deadlines, and developed new task partitioning techniques. Throughout our research, we have conducted extensive simulations to study the effectiveness and efficiency of our developed techniques.The increasing process variation and the ever-increasing scale and complexity of real-time systems both demand a paradigm shift in the design of real-time applications. Effectively dealing with the uncertainty in design of real-time applications is a challenging but also critical problem. Our research is such an effort in this endeavor, and we conclude this dissertation with discussions of potential future work.

show abstract