Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques

Abstract

Hardware synthesis is the process by which system-level, Register Transfer (RT)-level, or behavioral descriptions can be turned into real implementations, in terms of logic gates. Scheduling is one of the most time-consuming steps in the overall design flow, and may become much more complex when performing hardware synthesis from high-level specifications. Exploiting a single scheduling strategy on very large designs is often reductive and potentially inadequate. Furthermore, finding the "best" single candidate among all possible scheduling algorithms is practically infeasible. In this article we introduce a hybrid scheduling approach that is a preliminary step towards a comprehensive solution not yet provided by industrial or by academic solutions. Our method relies on an abstract symbolic representation of data flow nodes (operations) bound to control flow paths: it produces a more realistic lower bound during the prescheduling resource estimation step and speeds up slower but accurate heuristic scheduling techniques, thus achieving a globally improved result.

A Note for the Two Incremental Satisfiability Problem

“…This restriction is modeled by 3 binary clauses, in the following way: 3 ). There are 3*|E| binary clauses of this class.…”

“…Different methods have been applied to solve ISAT, among them, variations of the branch and bounds procedure, denoted as IDPL methods, which are usually based in the classical Davis-Putnam-Loveland (DPL) method. In a IDPL procedure, when adding new clauses, the procedure maintains the search tree generated previously for the set of clauses K. Rather than solving related formulas separately, modern solvers attempt to solve them incrementally since many practical applications require solving a sequence of related SAT formulas [3], [4].…”

“…Rather than solving related formulas separately, modern solvers attempt to solve them incrementally, since many practical applications require solving a sequence of related SAT formulas [3], [4]. In this article, we consider ISAT as an incremental problem that starts with an initial satisfiable formula K=F in 2-CNF.…”

Design space exploration for an embedded processor with flexible datapath interconnect

“…The question of when and where to buffer and read data to make sure that all operations are satisfied quickly becomes complex. The scheduler expresses dependencies between instructions as routing constraints and employs a SAT-solver [7], [8], [9] to find a solution, if one exists.…”