Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection

Gören, Sezer; Gürsoy, Cemil Cem; Yildiz, Abdullah

doi:10.1007/s10836-015-5544-2

Cited by 4 publications

(1 citation statement)

References 16 publications

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“…Therefore, fault-analysis based selection is highly impractical and cannot cope with large netlists, which are typically the ones worth protecting against counterfeiting. Emulation has been proposed in [25] to speed-up the process but it requires a very large FPGA for implementation since it increases the size of the original a lot. Moreover, the correlation value of 0.2 is obtained from only three combinational benchmarks, which are relatively small.…”

Section: Comparison With Existing Heuristicsmentioning

confidence: 99%

Centrality Indicators for Efficient and Scalable Logic Masking

Colombier

Bossuet

Hély

2017

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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International audienceModifying the logic at register transfer level can help to protect a circuit against counterfeiting or illegal copying. By adding extra gates, the outputs can be controllably corrupted. Then the circuit operates correctly only if the right value is applied to the extra gates. The main challenge is to select the best position for these gates, to alter the circuit's behaviour as much as possible. However, another major point is the computational efficiency of the selection process, which should be as good as possible for integration in EDA tools. State-of-the art methods, based on fault analysis, are very demanding and cannot cope with large netlists in a reasonable runtime. We propose to use centrality indicators instead. Centrality is used to identify the most significant vertices of a graph. We show that, when used to select the nodes to modify, they lead to low correlation between original and altered outputs while being computationally efficient. We give experimental results on combinational benchmarks and compare to other previously proposed heuristics. We show that this method is the only efficient selection heuristic which is able to handle large netlists and integrate smoothly into EDA tools

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Section: Comparison With Existing Heuristicsmentioning

confidence: 99%