Speeding up SAT-Based ATPG Using Dynamic Clause Activation

Eggergluss, Stephan; Tille, Daniel; Drechsler, Rolf

doi:10.1109/ats.2009.26

Cited by 9 publications

(3 citation statements)

References 17 publications

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“…The technique, presented in Tadesse et al [2011], used a SAT-based search algorithm to generate test patterns for stimulating worstcase critical paths for post-silicon debug. Others have used SAT to perform ATPG (e.g., [Eggersgluss et al 2009, Tille andDrechsler 2008]). …”

Section: Detecting Implication Coverage With a Sat Solvermentioning

confidence: 99%

Using implications to choose tests through suspect fault identification

Dworak

Nepal

Alves

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection techniques, including logic implication-based checker hardware, are capable of detecting at least some of these errors as they occur. However, recovery may be expensive, and the underlying problem may lead to multiple failures of a core over time. In this article, we will investigate the diagnostic capability of logic implications to identify possible failure locations when an error is detected online. We will then utilize this information to select a highly efficient test set that can be used to effectively test the identified suspect locations in both the failing core and in other identical cores in the system.

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Section: Detecting Implication Coverage With a Sat Solvermentioning

confidence: 99%

Using implications to choose tests through suspect fault identification

Dworak

Nepal

Alves

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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“…Various approaches to reduce the run-time of SATbased ATPG have stuck to this principle. A considerable reduction in SAT-solving time is achieved in [26] by using a central database to cache basic clauses as well as learnt clauses, hence allowing the sharing of SAT-instance portions and of learnt information between different SAT-instances. However, this approach still has to generate a new SAT-instance or to modify an existing SAT-instance for each new processed fault.…”

Section: Fault Clusteringmentioning

confidence: 99%

SAT-ATPG using preferences for improved detection of complex defect mechanisms

Czutro¹,

Sauer²,

Schubert³

et al. 2012

2012 IEEE 30th VLSI Test Symposium (VTS)

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Failures caused by phenomena such as crosstalk or powersupply noise are gaining in importance in advanced nanoscale technologies. The detection of such complex defects benefits from the satisfaction of certain constraints, for instance justifying specific transitions on neighbouring lines of the defect location. We present a SAT-based ATPGtool that supports the enhanced conditional multiple-stuck-at fault model (ECMS@). This model can specify multiple fault locations along with a set of hard conditions imposed on arbitrary lines; hard conditions must hold in order for the fault effect to become active. Additionally, optimisation constraints that may be required for best coverage can be specified via a set of soft conditions. The introduced tool justifies as many of these conditions as possible, using a mechanism known as SAT with preferences. Several applications are discussed and evaluated by extensive experimental data. Furthermore, a novel fault-clustering technique is introduced, thanks to which the time required to classify all stuck-at faults in a suite of industrial benchmarks was reduced by up to 65%.

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“…The new SAT technique Dynamic Clause Activation (DCA) is proposed in [ETD09] [ED10]. Using DCA, the SAT solver works on a subset of the original problem instance which is extended dynamically.…”

Section: A Dynamic Clause Activationmentioning

confidence: 99%

Robust algorithms for high quality Test Pattern Generation using Boolean Satisfiability

Eggersglüß

Drechsler

2010

2010 IEEE International Test Conference

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Abstract-Algorithms for Automatic Test Pattern Generation (ATPG) have to provide a high fault coverage in order to satisfy the quality demands of the chip industry. However, classical structural ATPG algorithms have problems to cope with the increased complexity of modern chip designs. The number of faults for which no test can be generated grows and the demands of the industry are compromised. New algorithms are necessary to retain the quality level. This results in a renewed interest in efficient ATPG algorithms which are fast and robust. ATPG algorithms based on Boolean Satisfiability (SAT) are a promising alternative to structural algorithms being very robust. However, SAT-based ATPG suffers from several limitations such as high run time or over-specified tests which prevent the use in industrial application.This paper proposes a SAT-based ATPG framework, which overcomes the limitations and allows for an efficient application in industrial practice. The framework is able to handle tri-state elements as well as unknown states. SAT formulations for the most prevalent fault models are proposed with special attention paid on the generation of high-quality tests. Novel techniques are introduced which boost the performance of the SAT-based ATPG process and reduce the number of unclassified faults to a minimum. Experimental results on large industrial circuits with multi-million elements show a significantly increased fault efficiency and very high fault coverage. The techniques presented make SAT-based ATPG suitable for the complexity of future designs and new complex fault models.

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Speeding up SAT-Based ATPG Using Dynamic Clause Activation

Cited by 9 publications

References 17 publications

Using implications to choose tests through suspect fault identification

Using implications to choose tests through suspect fault identification

SAT-ATPG using preferences for improved detection of complex defect mechanisms

Robust algorithms for high quality Test Pattern Generation using Boolean Satisfiability

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