Speeding Up the Decisions of Quad-Tree Structures and Coding Modes for HEVC Coding Units

Tai, Shen-Chuan; Chang, Chia Ying; Chen, Bo Jhih; Hu, Jui Feng

doi:10.1007/978-3-642-35473-1_40

Cited by 15 publications

(8 citation statements)

References 2 publications

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“…In [48], temporal correlation in neighbouring frames is exploited to reduce the number of quadtree splitting decisions. Based on the tree depth used in the co-localised CU in the previous frame and its neighbouring CUs, the encoder decides whether or not to split the current CU into sub-CUs.…”

Section: Coding Tree Structure Determinationmentioning

confidence: 99%

State of the Art on Computational Complexity of Video Encoders

Corrêa

Assunção

Agostini

et al. 2015

Complexity-Aware High Efficiency Video Coding

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This chapter presents an overview of the state-of-the-art research on computational complexity of video encoders. First, a description of current methods for modelling the computational complexity of state-of-the-art video encoders is presented. Then, methods for reducing and scaling the expenditure of computational resources in video codecs are presented. Finally, the conclusions of the chapter highlight the research challenges and open topics not fully addressed in the available literature.

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Section: Coding Tree Structure Determinationmentioning

confidence: 99%

State of the Art on Computational Complexity of Video Encoders

Corrêa

Assunção

Agostini

et al. 2015

Complexity-Aware High Efficiency Video Coding

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“…Reference [11] proposes a rate control scheme for region of interest (ROI) based on Fourier transform and neuron network. Reference [12] proposes an early SKIP mode decision, utilizing the characteristics of the SKIP mode to reduce the complexity. If the best prediction mode in the current CU depth and those of the reference CUs are SKIP mode, the procedure of the encoding CU can be terminated.…”

Section: Related Workmentioning

confidence: 99%

“…Th ES = µ ns + k ns σ ns (12) When the value of k s or k ns is larger, the probability of P s or P ns is lower. In contrast, the probability of P s (RD ≤ µ s − k s σ s ) or P ns (RD ≥ µ ns + k ns σ ns ) is higher when the value of k s or k ns is smaller.…”

Section: Accurate Rd-cost Thresholds Of Early Termination and Earlmentioning

confidence: 99%

“…In a summary, in this sub-section, we apply a one-sided Chebyshev's inequality to obtain the threshold for early termination (Th ET ) and the threshold for early split (Th ES ) as shown in (11) and (12). According to the statistical data, the 2-D hyperplanes are fitted by considering QP variations and CU sizes for acquiring proper parameters (k s and k ns ) of Th ES and Th ET , respectively.…”

Section: Accurate Rd-cost Thresholds Of Early Termination and Earlmentioning

confidence: 99%

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Acceleration for HEVC Encoder by Bimodal Segmentation of Rate-Distortion Cost and Accurate Determination of Early Termination and Early Split

et al. 2019

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The processing unit with a quad-tree structure in high efficiency video coding (HEVC/H.265) consists of a coding unit (CU), a prediction unit (PU), and a transform unit (TU). The CU and PU account for the majority of the computational complexity. This paper proposes a fast inter-prediction algorithm to overcome the high-computational demand associated with the coding complexity for an HEVC/H.265 encoder. In this paper, the CU depth prediction is proposed to reduce the number of CU executions by incorporating the depths and rate-distortion costs (RD-costs) of the adjacent CUs. Bimodal RD-cost segmentation is proposed for the elementary dichotomy of RD-cost distribution. The proposed algorithm applies the one-sided Chebyshev's inequality for the determination of accurate RD-cost thresholds by adjusting the error rates for early termination and early split. Our approach achieves 50.1% and 48.7% time savings with Bjøntegaard delta bit rate (BDBR) increases of 1.2% and 1.0% compared to the HEVC/H.265 reference software for random access and low delay configurations, respectively. The proposed method has better performance than earlier researches in terms of both coding speed and rate-distortion.

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“…CTU size is selected by the encoder and can be larger or smaller than a traditional macroblock [2]. Each CTU is partitioned into one or more code units (CUs), and each CU has an associated partitioning into prediction units (PUs) and a tree of transform units (TUs) [4]. Each PU is coded using either inter or intra prediction.…”

Section: Introductionmentioning

confidence: 99%

A highly parallel SAD architecture for motion estimation in HEVC encoder

Medhat

Shalaby

Sayed

et al. 2014

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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Abstract-The high computational cost of the motion estimation module in the new HEVC standard raises the need for efficient hardware architectures that can meet the real-time processing constraint. In addition, targeting HD and UHD resolutions increases the motion estimation processing cost beyond the capabilities of the currently existing architectures. This paper presents a highly parallel sum of absolute difference (SAD) architecture for motion estimation in HEVC encoder. The proposed architecture has 64 PUs operating in parallel to calculate the SAD values of the prediction blocks. It processes block sizes from 4x4 up to 64x64. The proposed architecture has been prototyped, simulated and synthesized on Xilinx Virtix-7 XC7VX550T FPGA. At 458 MHz clock frequency, the proposed architecture processes 30 2K resolution fps with ±20 pixels search range. The prototyped architecture utilizes 7% of the LUTs and 5% of the slice registers in Xilinx Virtex-7 XC7VX550T FPGA.

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Speeding Up the Decisions of Quad-Tree Structures and Coding Modes for HEVC Coding Units

Cited by 15 publications

References 2 publications

State of the Art on Computational Complexity of Video Encoders

State of the Art on Computational Complexity of Video Encoders

Acceleration for HEVC Encoder by Bimodal Segmentation of Rate-Distortion Cost and Accurate Determination of Early Termination and Early Split

A highly parallel SAD architecture for motion estimation in HEVC encoder

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