Spice-based performance analysis of ultra-low voltage Si nanowire CMOS circuits

Abstract

An ultra-low voltage performance of nanowiretransistors-based CMOS circuits is investigated using the Spice model parameters. All Spice model parameters of BSIM4 are extracted from measurement data of nanowire transistors fabricated on 300 mm SOI wafer. The delay time and the power consumption of NW-Tr.-based and bulk-Tr.-based CMOS circuits are examined. The operation voltage of NW-Tr.-based inverter is reduced 300 mV smaller than that of bulk-Tr.-based inverter due to the ideal sub-threshold slope. The performance benefits of NW-Tr.-based stacked circuit and SRAM cell are measured in terms of ultra-low voltage and ultra-low power operation.

BSIM4 parameter extraction for tri-gate Si nanowire transistors

“…The excellent gate controllability over the channel in the multi-gate structure leads to the ideal subthreshold slope and the strong immunity to short-channel effects [2]. Therefore, further voltage scaling with minimizing off-state leakage current (I off ) is expected for CMOS circuit with ultra-low power operation [3] [4].…”