SPICE Simulation of RRAM-Based Cross-Point Arrays Using the Dynamic Memdiode Model

Abstract

We thoroughly investigate the performance of the Dynamic Memdiode Model (DMM) when used for simulating the synaptic weights in large RRAM-based cross-point arrays (CPA) intended for neuromorphic computing. The DMM is in line with Prof. Chua’s memristive devices theory, in which the hysteresis phenomenon in electroformed metal-insulator-metal structures is represented by means of two coupled equations: one equation for the current-voltage characteristic of the device based on an extension of the quantum point-contact (QPC) model for dielectric breakdown and a second equation for the memory state, responsible for keeping track of the previous history of the device. By considering ex-situ training of the CPA aimed at classifying the handwritten characters of the MNIST database, we evaluate the performance of a Write-Verify iterative scheme for setting the crosspoint conductances to their target values. The total programming time, the programming error, and the inference accuracy obtained with such writing scheme are investigated in depth. The role played by parasitic components such as the line resistance as well as some CPA’s particular features like the dynamical range of the memdiodes are discussed. The interrelationship between the frequency and amplitude values of the write pulses is explored in detail. In addition, the effect of the resistance shift for the case of a CPA programmed with no errors is studied for a variety of input signals, providing a design guideline for selecting the appropriate pulse’s amplitude and frequency.

Effects of the voltage ramp rate on the conduction characteristics of HfO2-based resistive switching devices

“…which well describes the combined action of two physical mechanisms (generation/rupture and evolution of the CF). The solid lines of figure 10(a) represent this equation for the set and Interestingly, the initial CF generation and destruction phases are consistent with the predictions of the DMM [46,47], which considers the device memory state as a function of the electrical stimulus.…”

SPICE Implementation of the Dynamic Memdiode Model for Bipolar Resistive Switching Devices

“…Assuming an inverted parabolic potential barrier for the constriction's bottleneck (scatterer), T(E) is expressed as: Many of these models almost exclusively focus on the popular quasi-static, pinched I-V loop, ignoring the associated time-related dependencies. However, the latter has special relevance when considering real case application scenarios such as those described in [19], where the programming and reading of the device is made in terms of voltage pulses of varying frequency/duty cycle. In this regard, we aim to report the fundamentals and the SPICE implementation of a revised Dynamic Memdiode Model (DMM) for bipolar RS devices capable of incorporating the time-related dependencies, as well as the guidelines for its usage.…”

“…In this regard, we aim to report the fundamentals and the SPICE implementation of a revised Dynamic Memdiode Model (DMM) for bipolar RS devices capable of incorporating the time-related dependencies, as well as the guidelines for its usage. Since this new version incorporates a dynamic balance equation for the memory state and a higher level of details in terms of modelling accuracy, we consider that it is a breakthrough with respect to the previous models proposed by our group: the Quasi-static Memdiode Model (QMM) [20][21][22] and a first version of the DMM [19]. The first one relies on the double-diode circuit controlled by the Krasnosel'skii-Pokrovskii hysteresis operator [23].…”

“…The QMM can be used for arbitrary input signals, but the memory state is unable to evolve in the subthreshold regime. Seeking to overcome this limitation, we introduced the original DMM in [19].…”

Hardware implementation of memristor-based artificial neural networks

“…This procedure was successfully used to evaluate the accuracy, power dissipation, latency and other figures-of-merit of hardware-based neural networks during inference 250 , 253 . It also allows to study in detail the weight update process 254 and the mitigation of stuck-at-faults 255 . To speed up the simulation process, we rely for this implementation in the FastSPICE simulator from the Synopsys Design Suite, although it is perfectly compatible with standard H-SPICE.…”