Spidergon: a novel on-chip communication network

Abstract

The SoC (System on Chip) design demands for novel architectural and circuital solutions to cope with the global wires issue, pushing the on-chip communication as a crucial and precious resource. In the context of the communication centric paradigm and according to a layered based design, it is foreseen that current on-chip shared bus will be, at least partially, replaced by a micronetwork interconnection implementing a flexible packetbased communication [l]. We state that the availability of an efficient on-chip communication platform is one of the most important enabling factors for the development of efficient and cost effective multi processor SoC in the near and long-term future. This summarypresmts the low cost, high performance on-chip communication network, called Spidergon, developed by the AST fidvanced System Technology) of STMicroelectronics as the possible evolution of STBus technology.The main driving factor of the Spidergon research activity is to explore the complex design space to match a low cost hardware implementation. On that respect we performed the strategic choice of adopting a particular and fixed topology, to exploit the relevant properties for proposing an optimized NoC (Network on Chip) solution. Spidergon NoC is based on a novel scalable, regular, point-to-point topology. The Spidergon network connects a generic even number of nodes N=2n (n=2,3 ... ) as a hidirectional ring in both clockwise, and antklockwise directions uith in addition a cross connection for each couple of nodes. By a formal definition, each node i, with 05 i <N, is connected by three unidirectional links to other three nodes as follows: (i) clockwise, i.e. node i to node (i+l) mod N; ( i i ) anti-clockwise, i.e. node i to node (i-1) mod N; ( i ) cross, i.e. node i to node (itn) mod N. The key advantages of this topology are: a good network diameter; a low number of connections; homogeneous building blocks (the same router to compose the entire network of a generic N); a simple routing scheme.The Spidergon NoC implements a packet-based communication, adopting wormhole switching. Indeed wormhole scheme, with respect to virtual cut-through or store-forward, drastically reduces the amount of network buffering (queues with the flit granularity instead of packet) and allows for a deep pipelined packet communication. A deterministic, shortest-path routing algorithm has been defined for the Spidergon topology: the relevant implementation is very simple without posing the need for expensive routing tables and ensuring fast processing of the packet header. The idea is to move along the ring, in the proper direction, to reach nodes which are close of the source node (not far from dSN/41 hops), otherwise to use the cross link to be in part of the network that is far away. Two virtual channels in the ring links (clockwise and anticlockwise) allows to guarantee deadlock avoidance. The choice of a deterministic routing and virtual channel scheduling avoids costly disordered end-to-end transfers: the routing path of any packet does ...

Meeting Deadlines Cheaply

“…. , 7} equipped with a Spidergon network topology developed in ST [10] which is used in the XSTREAM architecture. A spidergon network has links of the form (i, i+1 mod 8), (i, i−1 mod 8) and (i, i+4 mod 8) for every i and there is a path of length at most 2 between any pair of processors.…”

“…We then pose the same problem where the communication channels are considered as additional resources occupied for durations proportional to the amount of transmitted data, thus incorporating data locality considerations. In this setting we can solve problems with 15-20 tasks on a spidergon topology [10] with up to 8 processors. Finally we formulate a periodic extension of the problem where task instances arrive every ω time units and must be finished within a relative deadline δ > ω.…”

Quarc: A Novel Network-On-Chip Architecture

“…The Spidergon NoC [16] is a network architecture which has been recently proposed by STMicroelectronics [20]. The objective of the Spidergon topology has been to address the demand for a fixed and optimized topology to realize low cost multi-processor SoC implementation.…”

“…Nostrum [18], AEthereal [9], and Xpipes [17] are some examples of architectures used for on-chip networks. The Spidergon NoC [16] is also one of the ring-based architectures proposed recently.…”

Exploration of distributed shared memory architectures for NoC-based multiprocessors

“…In this section, three different NoC topologies have been considered from the energy/delay perspective: ring, spidergon [23] and mesh. For the exploration, the memory-intensive Matrix benchmark has been executed by the target architecture by varying the number of distributed memory modules from 1 to 3 (corresponding to 13-to 15-node topologies).…”