SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture

Navaridas, Javier; Furber, Steve; Garside, Jim; Jin, Xin; Khan, Muhammad; Lester, David; Luján, Mikel; Miguel-Alonso, José; Painkras, Eustace; Patterson, Cameron; Plana, Luis A.; Rast, Alexander; Richards, Dominic; Shi, Yebin; Temple, Steve; Wu, Jian; Yang, Shufan

doi:10.1016/j.parco.2013.09.001

Cited by 10 publications

(7 citation statements)

References 38 publications

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“…This has motivated the development of various neuromorphic computing systems whose architectures reflect the general organizational principles of nervous systems in an effort to partially reproduce the immense efficiency advantage that biological computation exhibits in some problems. These neuromorphic systems are organized as populations of excitatory and inhibitory spiking neurons with configurable synaptic connections (FACETS, 2005–2009 ; Navaridas et al, 2013 ; Benjamin et al, 2014 ; Merolla et al, 2014 ; Ning et al, 2015 ).…”

Section: Introductionmentioning

confidence: 99%

Implementation of a spike-based perceptron learning rule using TiO2−x memristors

et al. 2015

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Synaptic plasticity plays a crucial role in allowing neural networks to learn and adapt to various input environments. Neuromorphic systems need to implement plastic synapses to obtain basic “cognitive” capabilities such as learning. One promising and scalable approach for implementing neuromorphic synapses is to use nano-scale memristors as synaptic elements. In this paper we propose a hybrid CMOS-memristor system comprising CMOS neurons interconnected through TiO2−x memristors, and spike-based learning circuits that modulate the conductance of the memristive synapse elements according to a spike-based Perceptron plasticity rule. We highlight a number of advantages for using this spike-based plasticity rule as compared to other forms of spike timing dependent plasticity (STDP) rules. We provide experimental proof-of-concept results with two silicon neurons connected through a memristive synapse that show how the CMOS plasticity circuits can induce stable changes in memristor conductances, giving rise to increased synaptic strength after a potentiation episode and to decreased strength after a depression episode.

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Section: Introductionmentioning

confidence: 99%

Implementation of a spike-based perceptron learning rule using TiO2−x memristors

et al. 2015

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“…The coding efficiency of the RZ Berger code protocol is quite straightforward to calculate (Equation 5). The variable k again denotes the number of parity bits as defined in Equation (2). However, since the code words of the Berger code have different Hamming weights the determination of the power metric is a little bit more involved.…”

Section: Delay-insensitive Codesmentioning

confidence: 99%

“…DI communication elegantly overcomes these problems: Here the data encoding is chosen such that the receiver can recognize when a code word is complete (i.e., all wires made their final transitions)-in the absence of an accompanying clock or valid signal, and even in the presence of arbitrary skew on the transmission link. Such links have been successfully employed in many applications, such as Spinnaker [2,3], or Chain [4].…”

Section: Introductionmentioning

confidence: 99%

Novel Approaches for Efficient Delay-Insensitive Communication

Huemer

Steininger

2019

JLPEA

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The increasing complexity and modularity of contemporary systems, paired with increasing parameter variabilities, makes the availability of flexible and robust, yet efficient, module-level interconnections instrumental. Delay-insensitive codes are very attractive in this context. There is considerable literature on this topic that classifies delay-insensitive communication channels according to the protocols (return-to-zero versus non-return-to-zero) and with respect to the codes (constant-weight versus systematic), with each solution having its specific pros and cons. From a higher abstraction, however, these protocols and codes represent corner cases of a more comprehensive solution space, and an exploration of this space promises to yield interesting new approaches. This is exactly what we do in this paper. More specifically, we present a novel coding scheme that combines the benefits of constant-weight codes, namely simple completion detection, with those of systematic codes, namely zero-effort decoding. We elaborate an approach for composing efficient “Partially Systematic Constant Weight” codes for a given data word length. In addition, we explore cost-efficient and orphan-free implementations of completion detectors for both, as well as suitable encoders and decoders. With respect to the protocols, we investigate the use of multiple spacers in return-to-zero protocols. We show that having a choice between multiple spacers can be beneficial with respect to energy efficiency. Alternatively, the freedom to choose one of multiple spacers can be leveraged to transfer information, thus turning the original return-to-zero protocol into a (very basic version of a) non-return-to-zero protocol. Again, this intermediate solution can combine benefits from both extremes. For all proposed solutions we provide quantitative comparisons that cover the whole relevant design space. In particular, we derive coding efficiency, power efficiency, as well as area effort for pipelined and non-pipelined communication channels. This not only gives evidence for the benefits and limitations of the presented novel schemes—our hope is that this paper can serve as a reference for designers seeking an optimized delay-insensitive code/protocol/implementation for their specific application.

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“…During the boot process, any malfunctioning core is excluded from the list of available cores. This is a part of fault tolerance mechanisms in SpiNNaker that take place in several levels to ensure reliability against system failure [5]. In our work, we also applied an additional mechanism such that malfunction cores can also be detected during run time by monitoring their activities.…”

Section: Spinnaker Chips and Machinesmentioning

confidence: 99%

High performance computing on SpiNNaker neuromorphic platform: A case study for energy efficient image processing

Sugiarto

Liu

Davidson

et al. 2016

2016 IEEE 35th International Performance Computing and Communications Conference (IPCCC)

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Abstract-This paper presents an efficient strategy to implement parallel and distributed computing for image processing on a neuromorphic platform. We use SpiNNaker, a manycore neuromorphic platform inspired by neural connectivity in the brain, to achieve fast response and low power consumption. Our proposed method is based on fault-tolerant finegrained parallelism that uses SpiNNaker resources optimally for process pipelining and decoupling. We demonstrate that our method can achieve a performance of up to 49.7 MP/J for Sobel edge detector, and can process 1600 x 1200 pixel images at 697 fps. Using simulated Canny edge detector, our method can achieve a performance of up to 21.4 MP/J. Moreover, the framework can be extended further by using larger SpiNNaker machines. This will be very useful for applications such as energy-aware and time-critical-mission robotics as well as very high resolution computer vision systems.

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SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture

Cited by 10 publications

References 38 publications

Implementation of a spike-based perceptron learning rule using TiO2−x memristors

Implementation of a spike-based perceptron learning rule using TiO2−x memristors

Novel Approaches for Efficient Delay-Insensitive Communication

High performance computing on SpiNNaker neuromorphic platform: A case study for energy efficient image processing

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