Split and design guidelines for double patterning

Wiaux, Vincent; Verhaegen, Staf; Cheng, Stone; Iwamoto, Fumio; Jaenen, Patrick; Maenhoudt, Mireille; Matsukawa, Takashi; Postnikov, Sergei V.; Vandenberghe, Geert

doi:10.1117/12.774104

Cited by 16 publications

(11 citation statements)

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“…Unfortunately, a stitch is known to be highly sensitive to the overlay error, causing bridging or pinching. synthesis/manufacturing [8], [14], [17], but cannot be effectively addressed due to their high design dependency.…”

Section: B Challenges In Dptmentioning

confidence: 99%

“…To bridge the gap between current immersion lithography and again-delayed EUV lithography, double patterning technology (DPT) receives large attention from industry and is regarded as a technically and practically viable alternative to achieve high resolution for 32/22nm nodes [1], [7], [8], [11], [13], [14], [17]. The key idea of DPT is to decompose a single layout into two masks in order to increase pitch size and improve depth of focus (DOF) [9], [15].…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, it is important to make a layout more decomposable with fewer stitches. There are only a few previous works on layout decomposition mainly from a mask synthesis perspective using a commercial simulator [8], design guidelines [17], and pattern matching [14]. However, all these works mainly focus on postdesign optimization, which may be too late for successful decomposition.…”

Section: Introductionmentioning

confidence: 99%

“…For remaining grids which are in the BG state, we color each one with the nearest color along the corresponding subpath in lines 10-15. Since there can be within-path conflicts, we also perform post-processing in line [16][17][18][19][20][21][22]. Once a path is colored, we shadow around the path in line 23, which is described in Algorithm 2, to update the states of nearby grids.…”

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confidence: 99%

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Double patterning technology friendly detailed routing

Cho¹,

Ban²,

Pan³

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-Double patterning technology (DPT) is a most likely lithography solution for 32/22nm technology nodes as of 2008 due to the delay of Extreme Ultra Violet lithography. However, it should hurdle two challenges before being introduced to mass production, layout decomposition and overlay error. In this paper, we present the first detailed routing algorithm for DPT to improve layout decomposability and robustness against overlay error, by minimizing indecomposable wirelength and the number of stitches. Experimental results show that the proposed approach improves the quality of layout significantly in terms of decomposability and the number of stitches with 3.6x speedup, compared with a current industrial DPT design flow.

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Section: B Challenges In Dptmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Double patterning technology friendly detailed routing

Cho¹,

Ban²,

Pan³

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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“…Stitches will cause yield loss and increase manufacturing cost due to overlay errors, which is 5 nm or 6 nm under current 32 nm double patterning lithography. Some mask misalignment direction [4] could be actually beneficial for printability. However, on the presence of various process uncertainties, such as dose, focus, and mask errors, the printed stitch width could be easily smaller than 25 nm and result in design failure.…”

mentioning

confidence: 99%

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization

Yuan

Yang

Pan

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Double patterning lithography (DPL) is considered as a most likely solution for 32 nm/22 nm technology. In DPL, the layout patterns are decomposed into two masks (colors), and manufactured through two exposures and etch steps. If the spacing between two features (polygons) is less than certain minimum coloring distance, they have to be assigned opposite colors. However, a proper coloring is not always feasible because two neighboring patterns within the minimum distance may be in the same mask due to complex pattern configurations. In that case, a feature may need to be split into two parts to resolve the conflict, resulting in stitch insertion which causes yield loss due to overlay and line-end effect. While previous layout decomposition approaches perform coloring and splitting separately, in this paper, we propose a simultaneous conflict and stitch minimization algorithm with an integer linear programming (ILP) formulation. Since ILP is in class NP-hard, the algorithm includes three speed-up techniques: 1) grid merging; 2) independent component computation; and 3) layout partition. In addition, our algorithm can be extended to handle design rules such as overlap margin and minimum width for practical use as well as off-grid layout. Our approach can reduce 33% of stitches and remove conflicts by 87.6% compared with two phase greedy decomposition.Index Terms-Double patterning lithography, integer linear programming, layout decomposition.

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