Split capacitor DAC mismatch calibration in successive approximation ADC

Chen, Yanfei; Zhu, Xiaolei; Tamura, Hirotaka; Kibune, Masaya; Tomita, Yoshihiro; Hamada, Tomoko; Yoshioka, Masato; Ishikawa, Kiyoshi; Takayama, Takeshi; Ogawa, J.; Tsukamoto, Sanroku; Kuroda, Tadahiro

doi:10.1109/cicc.2009.5280859

Cited by 125 publications

(44 citation statements)

References 3 publications

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“…The split-array topology was adopted to reduce area and dynamic power consumption. A static latched comparator was selected to minimize the kickback noise [14]. By controlling two switches connected each at top and bottom plate of the crDAC ( SW TOP and SW BOT ) with the right sequence described in Fig.…”

Section: Noise Shapingmentioning

confidence: 99%

A 13-bit noise shaping SAR–ADC with dual-polarity digital calibration

Park

Ghovanloo

2013

Analog Integr Circ Sig Process

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We present a new noise shaping method and a dual polarity calibration technique suited for successive approximation register type analog to digital converters (SAR-ADC). Noise is pushed to higher frequencies with the noise shaping by adding a switched capacitor. The SAR capacitor array mismatch has been compensated by the dual-polarity digital calibration with minimum circuit overhead. A proof-of-concept prototype SAR-ADC using the proposed techniques has been fabricated in a 0.5-μm standard CMOS technology. It achieves 67.7 dB SNDR at 62.5 kHz sampling frequency, while consuming 38.3μW power with 1.8 V supply.

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Section: Noise Shapingmentioning

confidence: 99%

A 13-bit noise shaping SAR–ADC with dual-polarity digital calibration

Park

Ghovanloo

2013

Analog Integr Circ Sig Process

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“…Another technique in the design that significantly reduces total capacitance is the use of split capacitor [6]. Split capacitor has its own drawback, that the capacitive structure is quite sensitive to the parasitic capacitance of the top plate of the bridge capacitor to ground, which can destroy the INL and DNL, thus the dynamic performance.…”

Section: Techniques For Small Total Capacitancementioning

confidence: 99%

A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS

Guo

et al. 2011

2011 9th IEEE International Conference on ASIC

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A low power 1 V 10-bit 100MS/s successive approximation register (SAR) analog-to-digital (ADC) converter is presented. The use of top-plate-sample switching procedure and split capacitive array dramatically reduces total capacitance and saves switching energy. As small total capacitance and split structure together make capacitive array highly sensitive to parasitic capacitance, its layout becomes the key of the ADC. High sampling rate leads to ultra-high logic control clock frequency, so a variable self-timed clock generator is implemented and logical optimization to improve conversion speed is done inside. Special cares are taken to prevent charge leakage caused by 65nm GP process from ruining the dynamic performance. The prototype was fabricated in a 65nm IP9M GP CMOS technology. Post simulation results show a peak SNDR of 58.364dB and 1.6m W total power consumption with a figure of merit (FOM) of 24D1conversion-step.

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“…8 Several other techniques have also been proposed to reduce the total capacitance of a C-DAC. Capacitor calibration techniques compensate for capacitor mismatch in the foreground 9 or background. 10 These calibration techniques correct errors by using digital postprocessing at the cost of additional power consumption.…”

Section: Introductionmentioning

confidence: 99%

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

Yen

Tsai

2017

Circuit Theory & Apps

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This paper presents an energy-efficient 12-bit successive approximation-register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary-window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spuriousfree dynamic range and signal-to-noise-and-distortion ratio. The ADC prototype occupies an active area of 0.12 mm 2 in the 0.18-μm CMOS process and consumes a total power of 0.6 mW from a 1.5-V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7-dB signal-tonoise-and-distortion ratio and 83-dB spurious-free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure-of-merit of 43 fJ/conversion-step. KEYWORDSA/D converter (ADC), binary window, D/A converter (DAC), successive approximation register (SAR)

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Split capacitor DAC mismatch calibration in successive approximation ADC

Cited by 125 publications

References 3 publications

A 13-bit noise shaping SAR–ADC with dual-polarity digital calibration

A 13-bit noise shaping SAR–ADC with dual-polarity digital calibration

A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

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