Split, overlap, stitching, and process design for double patterning considering local reflectivity variation by using rigorous three-dimensional wafer-topography and lithography simulation

Kamohara, Itaru; Schmöller, Thomas

doi:10.1117/1.3599858

Cited by 3 publications

(2 citation statements)

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“…However, this practice starts to hit its limit as the device feature sizes continue to shrink. The impact of wafer topography in a double-patterning process due to the first lithography step has been reported to reduce the process window of the second lithography step [9]. Studies have also shown that OPC is required to correct the problem of severe image distortions caused by wafer topography in implant processes [8].…”

Section: W3dmentioning

confidence: 98%

“…Both experimental studies and rigorous 3D wafer simulations have shown that the exposure image distortions caused by the underlying wafer topography are so severe for some features in an implant patterning process that OPC is required to correct the problem [8]. Wafer topography effects in double-patterning processes have also been reported [9].…”

Section: Introductionmentioning

confidence: 97%

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A full-chip 3D computational lithography framework

Liu¹,

Zhang²,

Lan³

et al. 2012

SPIE Proceedings

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3D lithography simulations capable of modeling 3D effects in all lithographic processes are becoming critical in OPC and verification applications as semiconductor feature sizes continue to shrink. These effects include mask topography, resist profile and wafer topography. In this work we present an efficient computational framework for full-chip 3D lithography simulations. Since fast modeling of mask topography effects has been studied for many years and is a relatively mature area, we will only briefly review a full-chip 3D mask model, Tachyon M3D, to highlight the importance and modeling requirements for accurate prediction of best focus variations among different device features induced by mask topography. We will focus our discussions on a full-chip 3D resist model, Tachyon R3D, its derivation and simplification from a full physical resist model. The resulting model form is fully compatible with the existing 2D resist model with added capabilities for resist profile and top loss prediction. A benchmark against the full physical model will be presented as well. We will also describe the development of a full-chip 3D wafer topography model, Tachyon W3D, and the preliminary results against rigorous simulations.

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Section: W3dmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 97%