Splitting kinetics of Si0.8Ge0.2 layers implanted with H or sequentially with He and H

Nguyen, P.; Bourdelle, K.K.; Aulnette, C.; Lallement, F.; Daix, N.; Daval, N.; Cayrefourcq, I.; Letertre, F.; Mazuré, C.; Bogumilowicz, Y.; Tauzin, A.; Deguet, C.; Cherkashin, Nikolay; Claverie, A.

doi:10.1063/1.3033555

Cited by 5 publications

(2 citation statements)

References 13 publications

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“…Especially, based on the surface blistering or exfoliation observed for H ion implanted Si, Bruel [4] has proposed a technique named ''smart-cut'' to fabricate high quality silicon-on-insulator (SOI) structures. Nowadays, this technique has been extended to synthesize various heterostructures based on gas ion implantation combined with bonding method [5,6]. Gas ion (He or H) induced layer transfer of semiconductor materials generally needs high fluence and thermal treatment temperature.…”

Section: Introductionmentioning

confidence: 99%

Surface damage versus defect microstructures in He and H ion co-implanted Si3N4/Si

Zhu

Liu²,

Wang

et al. 2012

Nuclear Instruments and Methods in Physics Research Section B:

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Section: Introductionmentioning

confidence: 99%

Surface damage versus defect microstructures in He and H ion co-implanted Si3N4/Si

Zhu

Liu²,

Wang

et al. 2012

Nuclear Instruments and Methods in Physics Research Section B:

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“…In another survey, Chao et al has studied the characteristics of hydrogen in Ge and its effects on the layer splitting process (11). Splitting kinetics for Si and Si 0.8 Ge 0.2 with hydrogen and hydrogen-helium implants is also investigated in (12). To date, Si on insulator (13), strained Si on insulator (6), Ge on insulator (7) and SiGe on insulator (14) ECS Transactions, 45 (6) 131-139 (2012) 10.1149/1.3700946 © The Electrochemical Society substrates as well as Si p-n junctions (5) have been fabricated using this technique.…”

Section: Introductionmentioning

confidence: 99%

Ge/Si p-n Diode Fabricated by Direct Wafer Bonding and Layer Exfoliation

et al. 2012

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We report on the formation and electrical characterization of current transport across a p-Ge to n-Si diode structure obtained by direct wafer bonding and layer exfoliation. A low temperature anneal at 400 °C for 30 minutes improved the forward characteristics of the diode. The I on /I off ratio > 5×10 4 and > 8×10 3 is obtained at -0.5 V and -1 V, respectively The carrier transport mechanism was analyzed based on the I-V and C-V measurements and direct tunneling is suggested as the transport mechanism. This fabrication technique using a low thermal budget (T ≤ 400 °C) is an attractive option for heterogeneous integration.

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Well‐Ordered Thin‐Film Nanopore Arrays Formed Using a Block‐Copolymer Template

Jung

Ross

2009

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Following Moore's law, the transistor density and hence the computing power of integrated circuits have scaled exponentially with time. [1] However, optical lithography technology, which has sustained Moore's law over the last half century, is reaching a limit in pattern resolution. Unconventional lithography techniques are therefore required to enable the next generations of microelectronic device fabrication. The critical requirements are scalability, high throughput, low cost, and compatibility with existing fabrication techniques.During the past decade, films of self-assembled diblock copolymers (BCPs) have attracted significant attention for lithography applications because they can generate ordered microdomains with sizes below 30 nm by thermodynamically driven microphase separation [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] In this application, 2D arrays or monolayers of microdomains are desirable to facilitate pattern transfer. [4,7,13,14,17] Typically, self-assembled BCP microdomain arrays possess only short-range order, and thus to make technologically useful structures with long-range order and accurate registration, BCPs may be templated using features formed by another lithography technique. [4,5,9,10,[13][14][15]17,18] The most common templates are chemical [5,15,19,20] or topographic [4,8,9,13,14,17] patterns defined by electron beam lithography or optical lithography. Chemical templates can regulate the orientation and position of BCP microdomains to high precision [5,15,19,20] in BCP films consisting of out-of-plane cylinders or lamellae, in which both blocks contact the chemically patterned substrate. Topographic patterns, with or without substrate surface functionalization, use spatial confinement to impose long-range ordering in BCPs of many morphologies including in-plane cylinders and spheres, [4,8,9,13,14,17] and can also form 3D assemblies, [21][22][23][24] including morphologies such as rings, spirals, disks, and hollow cylinders that are not found in bulk. [21][22][23]25,26] Of key importance is the ability to transfer patterns with good fidelity from block copolymers into a variety of materials, including metals that may be difficult to dry-etch. In this communication, we describe a simple route to fabricate thin films with well-ordered nanopores (antidot arrays) using self-assembled block-copolymer lithography and pattern transfer processes. Long-range ordering of a sphere-forming block copolymer is accomplished using a brush-coated 1D topographic template and solvent annealing, and the spheres are used to make nanoporous patterns through a pattern reversal process. Examples of Ti, Pt, Ta, W, silica, and magnetic Co and Ni antidot arrays are presented. A second image reversal process was used to form Ni dot arrays. This general method may be used to make a diverse range of nanoatterned films that can be useful in applications including via formation in integrated circuits, filters, plasmonic and photonic bandgap structures, catalysts, templates, sensors, and solar cells. [27]...

show abstract

Splitting kinetics of Si0.8Ge0.2 layers implanted with H or sequentially with He and H

Cited by 5 publications

References 13 publications

Surface damage versus defect microstructures in He and H ion co-implanted Si3N4/Si

Surface damage versus defect microstructures in He and H ion co-implanted Si3N4/Si

Ge/Si p-n Diode Fabricated by Direct Wafer Bonding and Layer Exfoliation

Well‐Ordered Thin‐Film Nanopore Arrays Formed Using a Block‐Copolymer Template

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