SPR

Friedman, Stephen; Carroll, Allan; Essen, Brian Van; Ylvisaker, Benjamin; Ebeling, Carl; Hauck, Scott

doi:10.1145/1508128.1508158

Cited by 94 publications

(6 citation statements)

References 9 publications

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“…Aside from the mappers within the CGRA-ME framework, there are various other works on CGRA mapping; for example, a simulated annealing-based method (DRESC [9] and SPR [10]), a reinforcement learning-based method [11], a ZDD-based method [12], as well as other methods like PathSeeker [13] and RAMP [14]. [11] reports average runtimes of ∼100 seconds on DFGs of similar size to ours.…”

Section: Related Workmentioning

confidence: 95%

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors

Zhou,

Stojilović,

Anderson

2023

2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)

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A graph H is a minor of a second graph G if G can be transformed into H by two operations: 1) deleting nodes and/or edges, or 2) contracting edges. Coarse-grained reconfigurable array (CGRA) application mapping is closely related to the graph minor problem, where H is the application's dataflow graph and G is the CGRA's devicemodel graph. A heuristic algorithm to find graph minors has proven to be practical for sparse graphs with hundreds of vertices in a quantum computing application. In this work, we adapt the heuristic to CGRA application mapping, where the graphs have directed edges, and the vertices have unique types (e.g., representing ALUs or interconnect). Additionally, we alter the original cost function, taking inspiration from PathFinder, an iterative negotiated-congestion routing algorithm. In an experimental study comparing with a CGRA mapper based on integer linear programming, we demonstrate a higher rate of successful mappings and from 80× to up to orders of magnitude lower runtime.

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Section: Related Workmentioning

confidence: 95%

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors

Zhou,

Stojilović,

Anderson

2023

2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)

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“…While the ILP and SAT methods mentioned above try to solve placement and routing at the same time, this work splits them up somewhat, like [5], [14], [17], [18] or typical FPGA mapping approaches. The aim is to break-up one intractable problem into smaller tractable problems, but CGRAs have resisted this by having inflexible routing, as evidenced by the long runtimes of [5], [17]. The approach presented here is more of a hybrid, explicitly modelling hard routing constraints during placement, and then checking feasibility in a detailed routing step.…”

Section: Related Workmentioning

confidence: 99%

Generic Connectivity-Based CGRA Mapping via Integer Linear Programming

Walker

Anderson

2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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Coarse-grained reconfigurable architectures (CGRAs) are programmable logic devices with large coarsegrained ALU-like logic blocks, and multi-bit datapath-style routing. CGRAs often have relatively restricted data routing networks, so they attract CAD mapping tools that use exact methods, such as Integer Linear Programming (ILP). However, tools that target general architectures must use large constraint systems to fully describe an architecture's flexibility, resulting in lengthy run-times. In this paper, we propose to derive connectivity information from an otherwise generic device model, and use this to create simpler ILPs, which we combine in an iterative schedule and retain most of the exactness of a fully-generic ILP approach. This new approach has a speed-up geometric mean of 5.88× when considering benchmarks that do not hit a time-limit of 7.5 hours on the fully-generic ILP, and 37.6× otherwise. This was measured using the set of benchmarks used to originally evaluate the fully-generic approach and several more benchmarks representing computation tasks, over three different CGRA architectures. All run-times of the new approach are less than 20 minutes, with 90th percentile time of 410 seconds. The proposed mapping techniques are integrated into, and evaluated using the open-source CGRA-ME architecture modelling and exploration framework [1].

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“…Multithreading enables CGRAs to take advantage of thread-level parallelism in addition to instruction-level parallelism, and therefore maximize CGRA utilization and eventually the power efficiency of the system. Hamzeh et al [2012] and Hamzeh et al [2013] develop a recompilation-based heuristic to increase the applicability of CGRA-based parallel computation on a wide range of applications.…”

Section: Multithreading On Cgrasmentioning

confidence: 99%

A Software Scheme for Multithreading on CGRAs

Pager

Jeyapaul

Shrivastava

2015

ACM Trans. Embed. Comput. Syst.

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Recent industry trends show a drastic rise in the use of hand-held embedded devices, from everyday applications to medical (e.g., monitoring devices) and critical defense applications (e.g., sensor nodes). The two key requirements in the design of such devices are their processing capabilities and battery life. There is therefore an urgency to build high-performance and power-efficient embedded devices, inspiring researchers to develop novel system designs for the same. The use of a coprocessor (application-specific hardware) to offload power-hungry computations is gaining favor among system designers to suit their power budgets. We propose the use of CGRAs (Coarse-Grained Reconfigurable Arrays) as a power-efficient coprocessor. Though CGRAs have been widely used for streaming applications, the extensive compiler support required limits its applicability and use as a general purpose coprocessor. In addition, a CGRA structure can efficiently execute only one statically scheduled kernel at a time, which is a serious limitation when used as an accelerator to a multithreaded or multitasking processor. In this work, we envision a multithreaded CGRA where multiple schedules (or kernels) can be executed simultaneously on the CGRA (as a coprocessor). We propose a comprehensive software scheme that transforms the traditionally single-threaded CGRA into a multithreaded coprocessor to be used as a power-efficient accelerator for multithreaded embedded processors. Our software scheme includes (1) a compiler framework that integrates with existing CGRA mapping techniques to prepare kernels for execution on the multithreaded CGRA and (2) a runtime mechanism that dynamically schedules multiple kernels (offloaded from the processor) to execute simultaneously on the CGRA coprocessor. Our multithreaded CGRA coprocessor implementation thus makes it possible to achieve improved power-efficient computing in modern multithreaded embedded systems. ACM Reference Format:Jared Pager, Reiley Jeyapaul, and Aviral Shrivastava. 2015. A software scheme for multithreading on CGRAs.

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SPR

Cited by 94 publications

References 9 publications

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors

Generic Connectivity-Based CGRA Mapping via Integer Linear Programming

A Software Scheme for Multithreading on CGRAs

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