Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit    Modulator-Controlled Fractional PLL

Kokubo, Masaru; Kimura, Takashi; Oshima, Takashi; Noto, Takayuki; Suzuki, Mariko; Suzuki, Shigeyuki; Hirose, Takashi; Tomoaki, Takahashi; Jun, Kasai

doi:10.1093/ietele/e89-c.11.1682

Cited by 13 publications

(9 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…generators [11]. We can clearly notice the effect of noise (generating a slope at 30 dB/dec in agreement with Leeson's model [31]) in the range between the PLL closed-loop bandwidth and approximately 400 kHz, which is not present in [11].…”

Section: Measurement Resultssupporting

confidence: 82%

“…We can clearly notice the effect of noise (generating a slope at 30 dB/dec in agreement with Leeson's model [31]) in the range between the PLL closed-loop bandwidth and approximately 400 kHz, which is not present in [11]. At frequencies greater than 400 kHz, the value shown in Fig. 14 is about 8 dB larger than the phase noise measured in [11]. Yet, if we take into account that our VCO has a working frequency double with respect to [11], and that, according to almost all merit figures (as, for example, in the International Technology Roadmap for Semiconductors 2003), the phase noise increases at 20 dB/dec with the oscillating frequency, the actual difference is only a few decibels.…”

Section: Measurement Resultssupporting

confidence: 82%

Section: Measurement Resultssupporting

confidence: 77%

See 2 more Smart Citations

A 3-GHz Serial ATA Spread-Spectrum Clock Generator Employing a Chaotic PAM Modulation

Pareschi

Setti

Rovatti

2010

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

In this paper, we propose a prototype of a spread-spectrum clock generator which is the first known specifically meant generator for 3-GHz Serial Advanced Technology Attachment II (SATA-II) applications. A further innovative aspect of our prototype is that it takes advantage of a chaotic pulse-amplitude modulation as driving signal, instead of a triangular signal as in all spread-spectrum generators proposed so far in the literature for SATA-II. In this way, we are able to obtain the optimal theoretical electromagnetic-interference reduction by avoiding the periodicity of the modulated clock and completely flattening the peaks in the power spectral density. We also show that, despite the fact that such an unconventional aperiodic modulating signal is used, the clock can be recovered by exploiting a standard clock and data recovery circuit at the receiver side of the SATA-II bus. The circuit prototype has been implemented in 0.13-m CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW kHz, which is better than any other prototypes presented in the literature. The estimated random jitter is 5.4 ps , while the chip active area is mm and the power consumption is as low as 14.7 mW.

show abstract

Section: Measurement Resultssupporting

confidence: 82%

Section: Measurement Resultssupporting

confidence: 82%

Section: Measurement Resultssupporting

confidence: 77%

See 1 more Smart Citation

A 3-GHz Serial ATA Spread-Spectrum Clock Generator Employing a Chaotic PAM Modulation

Pareschi

Setti

Rovatti

2010

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…As a result, a popular SSCG configuration is based on a Δ-Σ modulated fractional-N frequency synthesizer, such as shown in Fig. 1 [6]- [10], with a periodic modulation profile. A Δ-Σ modulated technique is employed to modulate the integer-N divider and produces a triangular waveform with a small deviation as a control signal.…”

Section: Traditional Fractional-n Frequency Synthesizers With δ-σ Modmentioning

confidence: 99%

“…The common technique to produce SSCG is to apply and insert modulation into a phase-locked loop (PLL). The frequency can be modulated by imposing a signal on the control node of a voltage-control oscillator (VCO) [4], [5], or using a fraction-N technique to change the divider ratio to produce the modulation [6]- [10]. Usually, an oversampling Δ-Σ modulator can be used to interpolate the control signal of the programmable divider [11], [12].…”

Section: Introductionmentioning

confidence: 99%

A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology

Yang

Chang

Wong³

2008

IEICE Transactions on Fundamentals of Electronics, Communicatio

View full text Add to dashboard Cite

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N-1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2 GHz, the measured peak power reduction is around 16 dB for a deviation of 0.37% and a frequency modulation of 33 kHz. The circuit occupies 1.4 × 1.4 mm 2 in a 0.18-μm CMOS process and consumes 52 mW.

show abstract

A New Spread Spectrum Clock Generator for SATA Using Double Modulation Schemes

Hsieh

Kao

2007

2007 IEEE Custom Integrated Circuits Conference

View full text Add to dashboard Cite

Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit Modulator-Controlled Fractional PLL

Cited by 13 publications

References 0 publications

A 3-GHz Serial ATA Spread-Spectrum Clock Generator Employing a Chaotic PAM Modulation

A 3-GHz Serial ATA Spread-Spectrum Clock Generator Employing a Chaotic PAM Modulation

A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology

A New Spread Spectrum Clock Generator for SATA Using Double Modulation Schemes

Contact Info

Product

Resources

About