Spur-free all-digital PLL in 65nm for mobile phones

Staszewski, Robert Bogdan; Waheed, K.; Vemulapalli, S.; Dulger, F.; Wallberg, J.; Hung, Chih‐Ming; Eliezer, Oren

doi:10.1109/isscc.2011.5746215

Cited by 22 publications

(7 citation statements)

References 4 publications

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“…A model of an all-digital frequency synthesiser with included noise sources in the s-domain is shown in Figure 1 [10,11]. The main blocks are a phase detector, digitally controlled oscillator (DCO) and filter.…”

Section: Phase Noise In All-digital Frequency Synthesisersmentioning

confidence: 99%

“…The ∆Σ dithering frequency and order of ∆Σ modulator are not provided, therefore we assume that the ∆Σ dithering frequency is equal to the DCO's frequency divided by 4, and the order of the ∆Σ modulator is 2nd. Phase noise of the reference signal and oscillator's component of DCO's noise are approximated respectively by Equations (9) and (10).…”

Section: Requirements For Blocks Of All-digital Multiband Frequency Smentioning

confidence: 99%

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Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications

Jurgo

Navickas

2018

Electronics

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In recent years number of Internet of Things (IoT) services and devices is growing and Internet of Vehicles (IoV) technologies are emerging. Multiband transceiver with high performance frequency synthesisers should be used to support a multitude of existing and developing wireless standards. In this paper noise sources of an all-digital frequency synthesiser are discussed through s-domain model of frequency synthesisers, and the impact of noise induced by main blocks of synthesisers to the overall phase noise of frequency synthesisers is analysed. Requirements for time to digital converter (TDC), digitally controlled oscillator (DCO) and digital filter suitable for all-digital frequency synthesiser for IoT and IoV applications are defined. The structure of frequency synthesisers, which allows us to meet defined requirements, is presented. Its main parts are 2D Vernier TDC based on gated ring oscillators, which can achieve resolution close to 1 ps; multi core LC-tank DCO, whose tuning range is 4.3–5.4 GHz when two cores are used and phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier; digital filter made of proportional and integral gain stages and additional infinite impulse response filter stages. Such a structure allows us to achieve a synthesiser’s in-band phase noise lower than −100 dBc/Hz, out-of-band phase noise equal to −134.0 dBc/Hz and allows us to set a synthesiser to type-I or type-II and change its order from first to sixth.

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Section: Phase Noise In All-digital Frequency Synthesisersmentioning

confidence: 99%

Section: Requirements For Blocks Of All-digital Multiband Frequency Smentioning

confidence: 99%

Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications

Jurgo

Navickas

2018

Electronics

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“…To characterize linearity, integral nonlinearity (INL) is an important metric for a DTC, similar to digital-to-analog converters (DAC). Non-zero DTC INL limits the achievable spur level in fractional-N PLLs [1]- [3] [16] and the timing accuracy in sampling oscilloscopes.…”

Section: Introductionmentioning

confidence: 99%

“…1). Switched capacitors [1][2] [4] or switched current sources [3][6] [7] can be applied to program delay.…”

Section: Introductionmentioning

confidence: 99%

A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging

Palattella

Geraedts

et al. 2015

IEEE J. Solid-State Circuits

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“…One practical limitation of ADPLLs is fractional spurs, which occur when the PLL is in a fractional-N frequency relationship during which the frequency command word FCW = f V /f R is very close to an integer (i.e., so-called an "integer-N" channel) [2]. f V is the generated variable frequency output; f R is the input reference frequency.…”

Section: Introductionmentioning

confidence: 99%