Sputter deposited titanium disilicide at high substrate temperatures

Abstract

Titanium disilicide films were sputter deposited from a composite TiSi2.1 target on 〈111〉 bare silicon wafers both at room temperature and at 600 °C. The room temperature as-deposited films require a 900 °C sintering step to reduce their resistivity. On the other hand, the as-deposited 600 °C films are fully reacted, polycrystalline, have no oxygen contamination, large grain sizes, and are oxidation resistant. Further annealing of these films at 900 °C produces no changes in their crystal structure, composition, resistivity, or grain size.

The Effects of Titanium Silicide Formation on Dopant Redistribution

“…Such a rapid diffusion, probably along grain boundaries in the silicide, would be expected to leave an anomalously large surface peak, since the surface area of grain boundaries would be larger at the surface than at any cross section of the bulk. A word of caution must be added here, however, since the interface between two growing silicide layers could contain excess oxygen and carbon since those impurities have been shown to snowplow into the titanium ahead of the forming silicide (22,26,34,39,48,49,54). Each figure shows a dopant peak in the bulk of the silicide, presumably at the interface of the two growing silicides.…”

“…The presence of dopants in the silicon have been reported to impact silicide growth kinetics (9-11, 13, 14, 18, 20, 21, 26-28, 33, 44), lateral overgrowth (26), and the tern-perature dependence of the silicide resistivity (27): Conversely, the presence of the silicide has an impact on the doping profile (5-10, 13, 14, 16-22, 32, 37, 38, 42-44), dopant loss (6,8,13,22,37,44), contact resistance (9,38), diode leakage (5, 9-12, 24, 38, 40), breakdown (26), and damage removal (7,30,31). Silicides on top of poly-Si (polycrystalline-silicon) gate electrodes create additional problems associated with dopant loss from the poly-Si and resulting changes in work function, etch rate, and resistance (6,22,29,42,44,45).…”

The Fabrication of Thin, Freestanding, Single‐Crystal, Semiconductor Membranes

“…Etching solutions of hydrazine, pyrocatechol, and water; or ethylenediamine, pyrocatechol, and water; or sodium hydroxide; or potassium hydroxide all etch silicon in similar ways: they are all highly anisotropic, which means that they dissolve the (100) planes faster than the (110) planes, which in turn dissolve faster than the (111) planes. Etching solutions of hydrazine, pyrocatechol, and water; or ethylenediamine, pyrocatechol, and water; or sodium hydroxide; or potassium hydroxide all etch silicon in similar ways: they are all highly anisotropic, which means that they dissolve the (100) planes faster than the (110) planes, which in turn dissolve faster than the (111) planes.…”

“…This means that it will work only for particular orientations of silicon, namely, (100) oriented, and perhaps also (110) oriented silicon. This means that it will work only for particular orientations of silicon, namely, (100) oriented, and perhaps also (110) oriented silicon.…”

“…Stressed films.--A rather novel approach to peeling thin films of single-crystal semiconductors off substrate wafers was developed by Tanielian, et al (110). When metals are evaporated or sputtered onto semiconductors, enormous stress is produced at the interface between the metal and the semiconductor.…”