SRAM-Based PUF Reliability Prediction Using Cell-Imbalance Characterization in the State Space Diagram

Abstract

This work proposes a methodology to estimate the statistical distribution of the probability that a 6T bit-cell starts up to a given logic value in SRAM memories for PUF applications. First, the distribution is obtained experimentally in a 65-nm CMOS device. As this distribution cannot be reproduced by electrical simulation, we explore the use of an alternative parameter defined as the distance between the origin and the separatrix in the bit-cell state space to quantify the mismatch of the cell. The resulting distribution of this parameter obtained from Monte Carlo simulations is then related to the start-up probability distribution using a two-component logistic function. The reported results show that the proposed imbalance factor is a good predictor for PUF-related reliability estimation with the advantage that can be applied at the early design stages.

A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array

“…Silicon PUFs are considerably cheaper than similar solutions, which makes them particularly attractive for resource-constrained applications such as IoT. There are many different silicon PUF implementations proposed in the literature [1], with some examples being ring oscillator PUFs [2], arbiter PUFs [3] or SRAM PUFs [4].…”

“…The work presented in [18] is applicable for generic silicon PUFs as well and includes a term to account for temperature, but not aging. A model specifically made for SRAM PUFs is introduced in [4], where the parameters are obtained by fitting experimental data. However, once again the model does not account for environmental factors or aging.…”