SRAM bitline circuits on PD SOI: advantages and concerns

Kuang, J.B.; Ratanaphanyarat, S.; Saccamango, M.J.; Hsu, L.; Flaker, R.; Wagner, L.; Chu, Stephen M.; Shahidi, G.

doi:10.1109/4.585285

Cited by 20 publications

(14 citation statements)

References 8 publications

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“…Besides floating body effects, such as history dependence, transient effects in DRAMiSRAM access transistors, the reliability of memory systems can be affected by the parasitic bipolar transistor. In 1997 an IBM study has shown [5] under normal operating conditions, that their effects are small. Design considerations and specifications for SRAM Cells [SI can be summarised as follows: I Adequate cell stability for reliable operation Maximizing "drive" current to achieve high speed Minimum cell size for highest density Good manufacturability Minimum operating current for low power Use minimum dimensions where needed and non-minimum in other circuits for robustness These are oflen conflicting requirements and trade-off must he made specific to the application.…”

Section: Basic 4t Memory Cellsmentioning

confidence: 97%

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An SOI 4 transistors self-refresh ultra-low-voltage memory cell

Thomas

Amara

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

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Analog and digital subthreshold circuit design.have been investigated recently in some niche applications where performance is of secondary concern but Ultra-LowPower is needed. In this paper we propose a new four transistors self-refresh memory cell operating in the subthreshold region:. Our simulations using a Partially Depleted SO1 0.25pm technology show a good stability of the cell to process and temperature variations. Combining our memory cell with current sensing scheme and grounded bit-lines leads to good performance despite a very low supply voltage.

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Section: Basic 4t Memory Cellsmentioning

confidence: 97%

“…SO1 implementations outperform conventional bulk ones due to significant reduction of collective device junction capacitance on the bit-lines [ 5 ] . Partially depleted (PD) SO1 technology has already found application in large-scale SRAM integration [6] [7].…”

Section: Basic 4t Memory Cellsmentioning

confidence: 99%

An SOI 4 transistors self-refresh ultra-low-voltage memory cell

Thomas

Amara

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

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“…Reducing the junction capacitance thus directly reduces a major component of the bitline capacitance, which is a critical parameter limiting memory performance. For example, in the study presented in [2], the junction capacitance in the bulk silicon SRAM model was estimated to contribute 42.1 % of the total bitline capacitance at a temperature of 25 C. Moving to an SO1 design reduced the junction capacitance by 74.5%, which in turn reduced the bitline capacitance by 3 1.4%.…”

Section: Introductionmentioning

confidence: 99%

“…Access to FD-SO1 fabrication is being provided by MIT Lincoln Labs. [2]. Reducing the junction capacitance thus directly reduces a major component of the bitline capacitance, which is a critical parameter limiting memory performance.…”

Section: Introductionmentioning

confidence: 99%

Design of an embedded fully-depleted SOI SRAM

Sung

Koob²,

Brandon³

et al.

Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing

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We describe the design of an embedded 128-Kb Silicoti-OnInsulator (Sol) CMOS SRAM, which is integrated alongside an array of pitch-matched processing elements to provide massively-parallel data processing within one integrated circuit. A n experimental 0.25-pm filly-depleted SO1 process was used. The design and layout of the SO1 memory core and results from calibrated circuit simulations are presented. The impact of the floating body efSect is investigated f o r both memory reads and writes. We describe threshold mismatch eflects in the sense ampli$er that result from the Jloating body voltage. Floating body effects are compared against simulated results f o r an SRAM designed in a 0.25-p m partially -depleted SO1 process.

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“…The significant reduction in junction capacitance of SOI MOSFETs also reduces a major component of bitline capacitance, which is a critical parameter limiting SRAM performance [1]. Furthermore a steeper subthreshold slope permits trade off between power consumption and performance for SRAM cell design.…”

Section: Introductionmentioning

confidence: 99%

UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation

Samsudin

Cheng

Brown

et al.

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.

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Abstract:Intrinsic parameter fluctuations steadily increases with CMOS technology scaling. Around the 90nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs. Ultra Thin Body (UTB) SOI MOSFETs are expected to replace conventional MOSFETs for integrated memory applications due to superior electrostatic integrity and better resistant to some of the sources of intrinsic parameter fluctuations. To fully realise the performance benefits of UTB SOI based SRAM cells a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuation information into the compact model is developed. The impact on 6T SRAM static noise margin characteristics of discrete random dopants in the source/drain regions and body-thickness variations has been investigated for well scaled devices with physical channel length in the range of 10nm to 5nm. A comparison with the behaviour of a 6T SRAM based on a conventional 35nm MOSFET is also presented.

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SRAM bitline circuits on PD SOI: advantages and concerns

Cited by 20 publications

References 8 publications

An SOI 4 transistors self-refresh ultra-low-voltage memory cell

An SOI 4 transistors self-refresh ultra-low-voltage memory cell

Design of an embedded fully-depleted SOI SRAM

UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation

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